Infrastructure AI/ML Engineer for Memory Design, Characterization, and Yield Optimization
About The Position
The Central Engineering Group is seeking an Infrastructure AI/ML Engineer to lead development of agentic AI infrastructure workflows for memory design, characterization, and yield optimization. The role collaborates with memory designers and DFT experts to build workflows for developing embedded memories optimized for performance, power, area, design-for-test (DFT), and yield. The engineer will design and scale distributed multi-agent AI frameworks; coordinate autonomous, multi-step workflows across memory development, silicon bring-up, and yield analysis; and integrate LLM-based pipelines with EDA suites, in-house tools, and enterprise data repositories. The position also develops machine-learning approaches for scan-failure classification and predictive yield modeling using semiconductor process and test data, while working with design, EDA, and infrastructure teams to turn hardware methodologies into modular agentic workflows aligned with organizational targets and milestones.
Requirements
- 15+ years of progressive, relevant experience in memory design, DFT, silicon yield analysis, software architecture, and AI systems engineering.
- Master’s degree or Ph.D. in Electrical Engineering or Computer Engineering.
- Experience designing and characterizing embedded memory in advanced technology process nodes.
- Experience in compute-in-memory design and architecture.
- Experience architecting production-grade LLM applications, including multi-agent orchestration, function calling/tool use, and retrieval-augmented generation (RAG).
- Experience integrating agentic systems with enterprise tools, services, and knowledge sources, including building and consuming Model Context Protocol (MCP) servers and packaging reusable agent capabilities such as Agent Skills.
- Deep experience with agent orchestration frameworks such as LangGraph.
- Fundamental understanding of chip design methodologies, IP block development lifecycles, and verification environments.
- Hands-on familiarity with EDA tooling and frameworks from Synopsys, Cadence, and Siemens EDA, as well as SystemVerilog and UVM verification environments.
- High proficiency in Python and TCL and in system design concepts.
- Expertise in microservices architecture, REST APIs, Docker, Kubernetes, sandboxing, and config-driven workflow orchestration engine design.
- Experience establishing evaluation metrics, testing benchmarks, and safety guardrails for non-deterministic AI systems in high-stakes environments.
- Technical depth in vector databases and cloud-native containerized orchestration pipelines.
Responsibilities
- Conceptualize, architect, deploy, and scale distributed multi-agent AI frameworks for memory design workflows optimized for performance, power, area, and yield.
- Orchestrate autonomous agent executions for multi-step reasoning, task decomposition, and decision-making across memory development, silicon bring-up, and yield analysis.
- Integrate LLM-driven agent pipelines with EDA suites, custom in-house software tools, and enterprise data repositories.
- Develop and deploy ML models to classify scan failures, including Chain, Stuck-at, and Transition failures, and correlate them with DFT structures.
- Integrate Fab process parameters, PCM data, and E-test data to predict yield excursions.
- Collaborate with Memory Design Leads, EDA Tool Specialists, and Infrastructure Engineers to convert domain-specific hardware engineering methods into modular, goal-driven agentic workflows.
- Align AI workflow capabilities with organizational efficiency targets and technical milestones across the Central Engineering Group.
Benefits
- Discretionary annual bonus
- Competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements
- Medical, dental, and vision plans
- 401(k) participation with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company-paid holidays
- Paid sick leave and vacation time
- Paid Family Leave and other leaves of absence in accordance with applicable laws
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What This Job Offers
Job Type
Full-time
Career Level
Senior
