Infrastructure AI/ML Engineer for Memory Design, Characterization, and Yield Optimization

Broadcom•San Jose, CA

1d•$150,800 - $241,200

About The Position

The Central Engineering Group is seeking an energetic, visionary, and passionate Infrastructure AI/ ML Engineer to lead the Agentic AI Infrastructure development workflow for memory design, characterization, and yield optimization. In this role, you will collaborate with memory designers and DFT experts to build Agentic AI workflows that drive the development of state-of-the-art embedded memories optimized for PPA, DFT, and yield.

Requirements

Experience designing and characterizing embedded memory in advanced technology process nodes
Experience in compute-in-memory design and architecture
Experience architecting production-grade LLM applications: multi-agent orchestration, function-calling/tool-use, and retrieval-augmented generation (RAG).
Experience integrating agentic systems with enterprise tools, services, and knowledge sources – including building and consuming Model Context Protocol (MCP) servers, and packaging reusable agent capabilities (e.g., Agent Skills).
Deep experience with agent orchestration frameworks such as LangGraph.
Fundamental grasp of chip design methodologies, IP block development lifecycles, and verification environments.
Hands-on familiarity with industry-standard EDA tooling and frameworks from Synopsys, Cadence, and Siemens EDA, alongside System Verilog & UVM verification environments.
High proficiency in core programming languages and system design concepts, specifically Python and TCL.
Expertise in microservices architecture, REST APIs, Docker, Kubernetes, Sandboxing, and config-driven workflow orchestration engine design.
Proven experience establishing evaluation metrics, testing benchmarks, and safety guardrails for non-deterministic AI systems in high-stakes environments.
Technical depth in Vector Databases, and cloud-native containerized orchestration pipelines.

Responsibilities

Conceptualize, architect, deploy, and scale robust, distributed multi-agent AI frameworks tailored to transform intricate memory design workflows optimized for performance, power, area, and yield
Orchestrate long-horizon, autonomous agent executions capable of managing multi-step reasoning, task decomposition, and decision-making across all phases of memory design development, silicon bring-up, and yield analysis
Seamlessly integrate Large Language Model (LLM)-driven agent pipelines with core Electronic Design Automation (EDA) suites, custom in-house software tools, and enterprise data repositories.
Develop and deploy ML models to automate the classification of scan failures (Chain, Stuck-at, Transition) and correlate them with design-for-test (DFT) structures.
Integrate high-dimensional data—including Fab process parameters, PCM (Process Control Monitoring), and E-test data—to predict yield excursions before they hit the assembly line.
Partner collaboratively with Memory Design Leads, EDA Tool Specialists, and Infrastructure Engineers to distill complex, domain-specific hardware engineering methodologies into modular, goal-driven agentic workflows.
Align AI workflow capabilities directly with organizational efficiency targets and technical milestones across the Central Engineering Group.