Infinity Fabric Senior Staff Verification Engineer
About The Position
The Infinity Fabric transport layer verification team is looking for a senior pre-silicon verification engineer to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed across Client, Server, Graphics, and Semi-Custom markets. You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
Requirements
- Proficient in IP level ASIC verification
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Good working knowledge of SystemC and TLM with some related experience.
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Experience working with complex designs (not just I2C and other similar designs).
- BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science preferred.
Responsibilities
- Define and drive verification strategy for complex GPU features or subsystems with cross‑project and cross‑product impact
- Partner with architects, RTL, and firmware leads to influence feature definition, implementation approach, and verification readiness early in the design cycle
- Own verification planning and execution for technically critical areas, including risk identification, trade‑off analysis, and mitigation strategies
- Lead development of robust, scalable verification environments and methodologies, including directed and constrained‑random testing using SystemVerilog and UVM
- Solve complex, ambiguous verification challenges, often requiring new approaches or extensions to existing processes and infrastructure
- Analyze functional and code coverage at a system level, driving coverage closure strategies that balance quality, schedule, and compute efficiency
- Drive improvements to verification processes, tools, and workflows that increase productivity, quality, or execution efficiency across teams
- Coordinate and technically lead small verification efforts within larger programs, aligning stakeholders and delivering on shared objectives
- Mentor and coach junior and senior engineers, acting as a go‑to technical resource and influencing best practices across the organization
Benefits
- AMD benefits at a glance
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
Associate degree
