IC Design Engineer

Broadcom • San Jose, CA

1d

About The Position

As a member of the Mixed-Signal ASIC Implementation team, you will be part of the team implementing new technologies from various exciting extremely low-power consumer electronic devices to high-performance Satellite projects. In addition, you will be directly involved with the following: Leading and implementing chips in various high-volume consumer devices to Satellite projects from ultra-low power 40nm nodes, 16nm to 7nm. Physical implementation of the blocks and top-level. Floorplanning including multi-power domain, PG planning, block-shaping & clock-tree implementation Interfacing with internal and external teams, including Design, IPs, and Library Physical Verification for block and chip-level Static and Dynamic IR drop Analysis. Signal and Power EM checks Methodology & Flow development of Physical Design & Timing Closure Working independently with the Synthesis & STA owners and RTL design team on Physical implementation and Power-intent requirements Knowledge of ESD, IO padring, Analog integration, and exposure to various types of packages, including flip-chip, wlcsp is a plus. Knowledge of AI tools preferable.

Requirements

• BS (Electrical)+ 12 years or MS (Electrical) +10 years of experience
• Multiple tapeouts experience and extensive hands-on knowledge in various tools such as Innovus, VCLP, Formality, LEC, timing closure, and Calibre.
• Cadence Innovus usage is essential.
• TCL scripting is required

Nice To Haves

• Knowledge of ESD, IO padring, Analog integration, and exposure to various types of packages, including flip-chip, wlcsp is a plus.
• Knowledge of AI tools preferable.
• Python is a plus

Responsibilities

• Leading and implementing chips in various high-volume consumer devices to Satellite projects from ultra-low power 40nm nodes, 16nm to 7nm.
• Physical implementation of the blocks and top-level.
• Floorplanning including multi-power domain, PG planning, block-shaping & clock-tree implementation
• Interfacing with internal and external teams, including Design, IPs, and Library
• Physical Verification for block and chip-level
• Static and Dynamic IR drop Analysis.
• Signal and Power EM checks
• Methodology & Flow development of Physical Design & Timing Closure
• Working independently with the Synthesis & STA owners and RTL design team on Physical implementation and Power-intent requirements

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 5,001-10,000 employees