Hardware/Software Integration Engineer (Compute Test, North Reading)

Teradyne•North Reading, MA

1d•$141,400 - $226,200•Onsite

About The Position

This role is for a Hardware/Software Integration Engineer specializing in Compute Test. The engineer will be responsible for tracing and resolving defects across the entire semiconductor test instrument stack, from application software to the physical hardware (ASICs and DACs). This involves understanding and debugging API calls, driver layers, embedded software, hardware abstraction layers, FPGA logic, and ASIC/DAC programming. The engineer will review code, RTL, and schematics beyond their direct deliverables, identify issues before hardware arrives, and facilitate communication between logic design, FPGA, and software engineering teams. The role also includes building and improving debug tooling, supporting internal diagnostic and calibration paths, aligning teams on failure models, verifying end-to-end system behavior, setting technical direction for cross-layer debugging, and partnering with vendors to resolve integration issues. Mentoring other engineers and expanding cross-disciplinary debugging capabilities are also key aspects of this position.

Requirements

Approximately 6+ years of engineering experience, including ownership across firmware and application software on at least one shipped product.
Proficiency in C and/or C++ for embedded or Linux environments and Python for automation, tooling, and analysis.
Strong register-level debugging skills with the ability to interpret datasheets, register maps, and DAC/ADC behavior.
Demonstrated experience solving cross-layer system problems and driving root cause across organizational boundaries.
Experience influencing teams outside your formal reporting structure.
Ability to read schematics and understand analog intent, voltage ranges, current limits, protection mechanisms, and signal paths.
Working knowledge of SPI, I²C, UART, PCIe, and Ethernet/UDP.
Excellent written and verbal communication skills.
BS or MS in Computer Engineering, Electrical Engineering, Computer Science, or equivalent experience spanning hardware and software.
Curiosity and willingness to work outside of narrowly defined ownership boundaries.

Nice To Haves

Firmware or board bring-up experience, including bootloaders, BSPs, or device drivers.
Exposure to FPGA development flows and the ability to read HDL.
Semiconductor test, instrumentation, measurement, or automation experience.
Calibration systems and engineering-unit conversion experience.
AI-assisted debugging, code review, or log analysis experience.
Multi-processor embedded system experience.

Responsibilities

Trace and root-cause defects end to end across the instrument stack, from host application and driver API through embedded software, the hardware abstraction layer, FPGA and ASIC/DAC programming, and drive the fix in whichever layer owns it.
Own the correctness of translation layers, including API surfaces and enumerations, register maps, bitstream encodings, and calibration math that converts engineering units into DAC codes and back.
Review code, HDL and schematics beyond your own deliverables, including abstraction-layer source, FPGA logic, register map changes across board revisions, and power-on versus runtime initialization paths.
De-risk new board revisions before hardware arrives by reviewing initialization, connect/disconnect pathways, and break-before-make sequencing.
Build and improve debug tooling, instrumentation, unified timeline views, automated analysis workflows, and AI-assisted debug and log review capabilities.
Support internal diagnostic, calibration, continuity, and production verification paths alongside customer-facing APIs.
Align logic design, FPGA, embedded software, and applications teams around shared failure models and maintain knowledge-sharing documentation.
Work backward from customer use cases to verify end-to-end system behavior across the stack.
Set technical direction for cross-layer debugging and participate in design, code, and RTL reviews.
Partner with component and silicon vendors to resolve system-level integration issues.
Mentor engineers and help expand cross-disciplinary debugging capabilities across the organization.