Hardware Engineering, Sr Staff Engineer- 19027

Synopsys•US (non-CA) Off-Site, US (non-CA) Off-Site Office

19d•$141,000 - $211,000•Remote

About The Position

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. This role involves performing interconnect assessments using the latest modeling techniques to predict channel data rates and signal margins. You will assess strategies for system performance optimization, including signal margins, power, and FFE, DFE, and CTLE equalization techniques. Additionally, you will assess power delivery systems to optimize power integrity for supply stability and jitter minimization. Responsibilities include documenting findings in reports and design guidelines, communicating results and insights to design teams to improve PHY design, and communicating results and recommendations to customers to enable them to optimize their system performance. You will interact with design teams and customers to refine and apply signal and power analysis methods to refine strategies and address problems. Understanding Synopsys’ DDR and HBM PHY roadmap and creating strategies for improved performance is key. Tracking industry developments through activities at standards committees and through memory vendor roadmaps is also a crucial part of the role. The R&D circuits team is tasked with providing SIPI solutions for the future DDR/HBM topologies and protocols, identifying key enablers, and providing support to early adopters or critical customers. We are also responsible for SIPI methodologies to be adopted by the customers and interconnect budgeting.

Requirements

Over 8+ years of experience in DDR/HBM SIPI engineering.
Deep understanding of high-speed interface signaling operations, including s-parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modeling.
Expertise in signal and power integrity analysis methods, such as eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysis.
Proficient in using HFSS and Ansys tools, HSPICE, Raptor, and ADS.
Skilled in generating and communicating results, findings, conclusions, and recommendations within a design team and to external customers.
Knowledge in board-level construction and on-chip IO design operation.
Ability to work seamlessly across multi-site teams, communicating ideas, understanding problems, and finding solutions to create leading-edge designs.
Proven understanding of high-speed interface signaling operation, such as s-parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modeling.
Well-versed in signal and power delivery analysis methods, including eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysis.
Ability to use HFSS and Ansys tools, HSPICE, Raptor, and ADS.
Skilled in generating and communicating results, findings, conclusions, and recommendations within a design team and to external customers.
Knowledgeable in board-level construction and on-chip IO design operation.

Nice To Haves

Team player able to communicate clearly and efficiently.
Ability to independently lead issues to full closure.

Responsibilities

Perform interconnect assessments using the latest modeling techniques to predict channel data rates and signal margins.
Assess strategies for system performance optimization, including signal margins, power, and FFE, DFE, and CTLE equalization techniques.
Assess power delivery systems to optimize power integrity for supply stability and jitter minimization.
Document findings in reports and design guidelines.
Communicate results and insights to design teams to improve PHY design.
Communicate results and recommendations to customers to enable them to optimize their system performance.
Interact with design teams and customers to refine and apply signal and power analysis methods to refine strategies and address problems.
Understand Synopsys’ DDR and HBM PHY roadmap and create strategies for improved performance.
Track industry developments through activities at standards committees and through memory vendor roadmaps.