Hardware Design Engineer

QualcommSan Diego, CA
$94,200 - $141,200

About The Position

As a Hardware Design Engineer, you will join an inventive team responsible for developing next-generation 6G prototype platforms and high-performance hardware modules. This role sits at the intersection of circuit design and physical validation, taking high-speed digital designs from initial schematic architecture through physical PCB layout oversight and lab testing. You will collaborate closely with global, cross-functional teams (including PCB CAD, Signal Integrity, Firmware, Mechanical, and Thermal) to deliver high-quality hardware solutions.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • 1–2 years of professional hardware engineering or related product-development work experience.
  • Demonstrated hands-on experience using lab test equipment (e.g., high-bandwidth digital oscilloscopes, logic analyzers, and multimeters) to isolate and troubleshoot hardware issues.
  • Fundamental knowledge of high-speed digital board design principles, including impedance control, crosstalk, and power delivery.

Nice To Haves

  • Master's degree in Electrical Engineering or Computer Engineering.
  • Experience utilizing schematic capture tools and basic simulation software (e.g., Hyperlynx, LTspice).
  • Hands-on familiarity with professional PCB layout software suites, such as Siemens/Mentor Xpedition or Cadence Allegro.
  • Basic understanding of high-speed interfaces such as Ethernet, PCIe, DDR, USB, or I2C/SPI protocols.

Responsibilities

  • Drive schematic capture, select hardware components, and manage complex bills of materials (BOMs) for multi-layer digital designs.
  • Oversee and actively participate in the physical PCB layout process, ensuring strict compliance with high-speed digital routing rules and constraints.
  • Perform physical board bring-up, debugging, and functional characterization of prototype hardware in the lab.
  • Collaborate with internal Signal Integrity and Power Integrity teams to optimize layout topologies for high-speed buses.
  • Document detailed test plans, validation reports, and hardware engineering change orders (ECOs).

Benefits

  • competitive annual discretionary bonus program
  • opportunity for annual RSU grants
  • highly competitive benefits package
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