FPGA Digital Design & Verification - Intern

Altera • San Jose, CA

1d • $95,000 - $100,000

About The Position

Altera is seeking a highly motivated Graduate Intern to join our FPGA Digital Design and Verification team. This internship provides hands-on experience working on industry-leading programmable logic devices, SoC platforms, and verification environments. The role is ideal for graduate students eager to grow their expertise in SystemVerilog, UVM-based verification, and digital design methodologies. You will collaborate with experienced engineers to design, verify, and validate RTL blocks and system-level features used in next-generation FPGA products.

Requirements

• Currently pursuing a Graduate Degree in Computer or Electrical Engineering or related field
• Strong foundation in Digital Logic Design and Computer Architecture
• Proficiency in SystemVerilog and Verilog
• Knowledge of UVM, functional coverage, constrained random verification, and assertions
• Experience using simulation and verification tools such as ModelSim, QuestaSim, or Synopsys VCS
• Familiarity with Linux-based development environments
• Ability to debug simulation issues and analyze waveforms effectively

Nice To Haves

• Hands-on project experience with UVM-based verification environments
• Experience verifying communication protocols (UART, SPI, AXI preferred)
• Exposure to FPGA tools such as Intel Quartus Prime or Xilinx Vivado
• Knowledge of SVA or formal verification concepts
• Programming or scripting experience in Python, Perl, Tcl, or C
• Exposure to HLS, SoC design, or hardware acceleration for AI/ML workloads

Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments for FPGA IPs and subsystems
• Create self-checking testbenches, constrained-random tests, and functional coverage models
• Write and debug SystemVerilog Assertions (SVA) to ensure protocol and design correctness
• Execute and analyze simulations using industry-standard EDA tools (VCS, QuestaSim, ModelSim)
• Assist in debugging RTL and verification failures, working closely with design engineers
• Verify common communication protocols (e.g., UART, SPI) and custom interconnects
• Contribute to documentation of verification plans, test strategies, and results
• Support FPGA-based systems including AI/ML accelerators, memory interfaces, and SoC components

What This Job Offers

• Career Level: Intern