FPGA Designer - TeraWave RF and Optical Systems Firmware

Blue Origin•Redmond, WA

2d•$157,419 - $220,387

About The Position

Blue Origin’s TeraWave program is seeking an FPGA Designer to design, verify, and integrate FPGA-based systems for high-speed data processing, communications, and signal-processing applications. The role owns project-level FPGA features from requirements through hardware integration and test, working on a small, multidisciplinary team. With clear technical direction and some oversight, the designer translates requirements into implementations, executes verification and timing closure, supports hardware integration, and communicates delivery risks and tradeoffs. The position calls for sound engineering judgment, clear documentation, and collaboration with systems, RF, avionics, thermal, hardware, software, manufacturing, and test engineers. The designer may also support qualification, acceptance testing, production troubleshooting, radiation testing, and on-orbit operations for owned designs as needed.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
Two or more years of hands-on FPGA design or verification experience, or an equivalent combination of graduate study and relevant engineering experience.
Proficiency in VHDL or Verilog/SystemVerilog for synthesizable RTL design and simulation.
Experience using an industry FPGA toolchain for synthesis, place-and-route, timing analysis, device programming, and debug.
Experience using UVM for FPGA design verification.
Working knowledge of high-speed digital design principles, including clock and reset design, clock-domain crossings, timing constraints, metastability, and resource optimization.
Experience developing testbenches and automated regression tests and diagnosing failures from simulation, implementation reports, and laboratory evidence.
Experience with laboratory board bring-up and debug using embedded logic analyzers, oscilloscopes, logic analyzers, or similar equipment.
Ability to develop technical estimates, identify risks, document design decisions, and deliver project-level assignments with limited day-to-day instruction.
Experience working with configuration management, requirements traceability, and formal or peer design reviews.
Strong written and verbal communication skills and ability to collaborate across engineering disciplines.
Applicants must be a U.S. citizen or national, U.S. permanent resident (current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

Nice To Haves

Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
Experience with AMD Versal, Microchip IGLOO, Intel, or equivalent FPGA and adaptive SoC families.
Experience implementing digital signal processing, modem, beamforming, network-processing, or high-speed communications functions in FPGAs.
Experience with PCIe, Ethernet, JESD204, high-speed SERDES, GTH or GTY transceivers, or comparable interfaces.
Experience with embedded processor integration and hardware-software co-design.
Experience applying and verifying space-grade single-event effect mitigation techniques or supporting radiation test and qualification activities.
Experience with formal verification, UVM-based verification, functional coverage, or constrained-random test methods.
Experience developing reusable IP, verification utilities, continuous-integration workflows, or automation using Python or Tcl.
Experience in a space, defense, satellite communications, or high-reliability product development environment.

Responsibilities

Own FPGA features through requirements analysis, technical design, RTL development, functional simulation, synthesis, place-and-route, timing closure, and hardware bring-up.
Translate allocated requirements into module architectures, interface definitions, implementation plans, verification objectives, and traceable design documentation.
Develop maintainable RTL in VHDL, Verilog, or SystemVerilog, and integrate vendor, third-party, or internally developed IP cores.
Develop and maintain verification environments using testbenches, assertions, automated regressions, constrained-random stimulus, or functional coverage as appropriate to design risk.
Analyze and resolve timing, resource utilization, clocking, reset, clock-domain crossing, and integration issues for designs of moderate complexity.
Implement and verify program-defined design-for-test, design-for-manufacturing, and space-grade reliability features, including single-event upset mitigation, triple modular redundancy, scrubbing, error-correcting codes, and fault detection where required.
Lead bring-up and debug for owned features; perform root-cause analysis of moderate-scope design or test nonconformances and develop and verify corrective actions.
Participate in preliminary, critical, peer, and test reviews as an author and reviewer, provide constructive feedback, and ensure review actions are closed.
Partner with systems, RF, avionics, thermal, hardware, software, manufacturing, and test engineers to define interfaces and validate end-to-end performance.
Estimate effort and complexity, identify technical and schedule risks, communicate progress, and recommend practical tradeoffs or mitigation plans.
Contribute improvements to FPGA coding standards, reusable IP, verification infrastructure, development workflows, and laboratory procedures.
Support qualification, acceptance testing, production troubleshooting, radiation testing, and on-orbit operations for owned designs as needed.

Benefits

Medical, dental, and vision insurance.
Basic and supplemental life insurance.
Paid parental leave.
Short- and long-term disability.
401(k) with company match of up to 5%.
Education Support Program.
Stock options for all regular employees working at least 20 hours per week.
Up to four weeks of paid time off per year based on weekly scheduled hours.
Up to 14 company-paid holidays.
Depending on role type and job level, employees may be eligible for benefits and bonuses based on individual contributions or company results; amounts and eligibility are not guaranteed and may change or be canceled.