FPGA Design Engineer

Associated Universities Inc. • Charlottesville, VA

1d • $90,015 - $126,000 • Onsite

About The Position

The National Radio Astronomy Observatory (NRAO), managed by Associated Universities, Inc. (AUI), is a leading research and development organization in radio astronomy. The Central Development Laboratory (CDL) at NRAO is seeking an experienced FPGA Design Engineer to join its digital design team. This role will support the design and implementation of a new digital signal processing system for a next-generation radio telescope synthesis array. The CDL's digital design team develops advanced systems that contribute to research in areas such as galaxy formation, star and planet origins, and black holes. The selected candidate will be involved in the design, implementation, and verification of embedded processor-based FPGA systems, with a strong emphasis on disciplined, timing-driven design and robust verification practices. This position is located at the Central Development Laboratory in Charlottesville, Virginia.

Requirements

• Bachelor’s degree in electrical engineering
• Five years of FPGA development experience in complex digital systems
• Strong proficiency in RTL design and hardware description languages
• Solid understanding of digital design fundamentals and FPGA implementation flows (synthesis through place-and-route)
• Experience with modern verification methodologies and design-for-verification practices
• Experience with embedded processor-based FPGA systems like (Intel Agile-X or similar) and high-speed or high-bandwidth interfaces
• Familiarity with DSP concepts and version control
• Strong problem-solving ability and effective written and verbal communication skills
• High level of competency in Microsoft software products and web-based systems, Visio and SharePoint.
• Attention to detail is critical
• Highly organized
• Excellent communication skills
• Observatory employees must be authorized to work in the United States. The Observatory presently cannot sponsor H-1B Visas for this position.

Responsibilities

• Design and implement embedded FPGA-based systems with a focus on performance, reliability, and timing closure
• Apply disciplined RTL design practices and sound synchronous design techniques, including management of clock domain crossings
• Develop and execute verification strategies, including self-checking testbenches and end-to-end system validation
• Perform static timing analysis, develop constraints, and drive designs to timing closure
• Translate algorithmic and DSP models into efficient FPGA implementations
• Contribute to reusable IP and scalable design architectures
• Work across multiple concurrent efforts, collaborating within a small, centralized team and with external partners
• Document designs, verification approaches, and technical decisions clearly

Benefits

• Excellent paid time off (13 holidays, annual accrual of up to 24 vacation days)
• Medical, dental and vision plans are effective on the first day of employment.
• AUI’s retirement benefit contributes an amount equal to 10 percent of a qualified participant’s base pay with no required employee contribution.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior