FPGA Design Engineer

Lockheed Martin•Orlando, FL

1d•Hybrid

About The Position

You will be the FPGA Design & Verification Engineer for the Lockheed Martin Advanced Technologies team. Our team creates cutting edge FPGA based solutions that power next generation defense and aerospace systems, delivering high performance computing, signal processing and real time control. As the FPGA Design & Verification Engineer you will capture and derive system requirements, design, simulate and integrate FPGA architectures, and develop verification environments. You will troubleshoot existing designs, implement updates, and build new FPGA solutions from concept through production, working closely with the Programmable Logic Design Lead and cross functional engineers.

Requirements

Bachelors degree from an accredited college in a related discipline, or equivalent experience/combined education
Relevant experience with FPGA design and simulation verification.
Familiarity of Synopsys EDA tools

Nice To Haves

LM Design Experience
Missile Experience
MSEE, MSCE would be a plus.
Experience with System-Verilog, Verilog, C/C++, MatLab / Simulink, System Verilog languages; Synopsis Synplify, Synopsis VCS, NCSim, ChipScope tool sets desired.
Experience with Xilinx/AMD and MicroSemi/Microchip part families internal FPGA fabric and IP.
FPGA design experience with tools noted above.
Previous experience related to aerospace design techniques would be a plus.
Prior experience with Lockheed Marin MFC is a plus
Experience Implementing NSA algorithms (i.e. AES, counter mode, etc)
Experience with management of Configuration Control (GitLab preferred)
Experience with Vivado, and Vitis FPGA toolsets
Experience with UVM
Experience with Simulink and HDL Coder
Comfortable using digital oscilloscopes, spectrum analyzers, power meters, signal generators and other test equipment
Experience with troubleshooting and debugging with board-level testing and FPGA validation
Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test)

Responsibilities

Translating system requirements into detailed FPGA designs, writing HDL code (SystemVerilog preferred, VHDL acceptable) and generating synthesis, placement, routing and timing constraints.
Developing self checking verification testbenches using SystemVerilog and UVM to validate functional behavior of each module.
Running simulations with Synopsys VCS, analyzing results, and iterating designs to meet performance, power and timing goals.
Managing source control and continuous integration pipelines in GitLab, tracking progress via GitLab Issues and maintaining version controlled design artifacts.
Collaborating with the Programmable Logic Design Lead and hardware, software and systems engineers to integrate FPGA designs into the overall product system.
Performing board level integration, debugging and troubleshooting of existing FPGA implementations, and delivering design updates as required.
Conducting timing analysis, power budgeting and resource utilization studies to optimize device selection and FPGA utilization.
Documenting design specifications, verification plans, test results and release packages in accordance with Lockheed Martin design assurance processes.
Supporting design review meetings, providing status updates and risk assessments to project leadership.
Mentoring junior team members on HDL coding, verification methodologies and GitLab workflow best practices.