Space Dynamics Laboratory (SDL) is seeking a junior FPGA design engineer to contribute to the design, fabrication, testing, and support of electronics for telecommunication hardware used in space vehicles and sensor payloads within our CVS Division. The role involves all aspects of payload algorithm discernment, development, optimization, and testing. The successful candidate will collaborate within larger electronics teams, both internal and external to SDL, and will be responsible for all phases of their assigned design block, from concept to integration and testing. The Civil & Commercial Space (CVS) Division is a leader in scientific research and space exploration, providing calibrated state-of-the-art sensors and satellites for major Government and commercial missions, along with advanced AI&T technologies and mission management. Projects span challenges in planetary science, Earth observation, heliophysics, and astrophysics. This is a full-time position located in Logan, UT.
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Job Type
Full-time
Career Level
Entry Level