Intel Foundry Process TD Frame CellSet Engineer

Intel Corporation•Hillsboro, OR

5d•Hybrid

About The Position

Intel Foundry Technology Development (TD) Frame Cellset Owner (FCO) team is looking for an individual responsible for the integration of scribeline cells (fab process monitors, litho alignment marks, litho metrology, electrical test, etc.) into frame layouts which accompany each product to support fabrication. The Frame Cellset Owner team works closely with many organizations including Process Technology Development, Product Design, Litho Resolution Enhancement Techniques, Design Enablement Runsets, Intel Tapeout Operations, Intel Mask Operations, and the Virtual Factory to enable all Intel process technologies both during development and continuing through high volume manufacturing. The Frame Cellset Owner team is responsible for the accuracy of all frame-related collaterals released.

Requirements

PhD in Electrical Engineering, Chemical Engineering, Materials Science, Industrial/Mechanical Engineering, or related field Or Masters Degree in Electrical Engineering, Chemical Engineering, Materials Science, Industrial/Mechanical Engineering, or related field, with 3+ years of semiconductor manufacturing experience Or Bachelor's Degree in Electrical Engineering, Chemical Engineering, Materials Science, Industrial/Mechanical Engineering, or related field, with 4+ years of semiconductor manufacturing experience
Experience in semiconductor manufacturing processes, particularly lithography and metrology.

Nice To Haves

1+ years of experience in one or more of the following: CAD layout tools, desirable are familiarity with Cadence Virtuoso and Calibre design software
Design flow
UNIX computing environments, and basic shell programming.

Responsibilities

Performing layout edits based on process design specifications and fab module owner guidelines.
Dispositioning drawn data changes through XORs and/or design rule flows.
Providing frame dimension and field configuration estimates to product design teams.
Verifying the placement of the scribe line cells in the frame to meet fab process module BKMs as well as technology design specifications.
Ensuring proper frame data output and validating the integrity of the frame through the tape out process.
Documenting and communicating frame revision changes and NPI setup data to manufacturing organizations through the Graphics website.