FE Engineering

Apple•Austin, TX

6d•Onsite

About The Position

Optimizing and Implementing designs for chips in hardware devices. Designing synthesis to convert functional Register Transfer Level code to digital logic gates in physical chip design. Performing Static timing analysis and constraint development to ensure that the physical design meets timing requirements. Working on Power integrity checks to ensure that the various power domains and their interfaces are complete. Working on Signoff checks to develop and maintain flows that help verify the overall quality of the chip designs. Engineering Change Order implementations to meet the overall functionality and timing closure of the design. Working with the CAD team and tool vendors to identify and quickly resolve any flow or integration issues. Creating innovative flows and processes to support new chip designs. Performing Lint checks, to ensure the overall quality of Register Transfer Level code meets the guidelines. Optimizing logic designs to achieve low power, low area, high performance and timing goals.

Requirements

Master’s degree or foreign equivalent in Electrical & Computer Engineering or related field and 2 years of experience in the job offered or related occupation.
Using VLSI design and timing to evaluate engineering tradeoffs.
Using knowledge of HDL to understand the functionality of the designs and suggest improvements.
Scripting in Perl and Python to automate tasks.
Using physical design concepts to improve timing, reduce congestion and to implement engineering change of orders (ECOs).
Using synthesis techniques and Boolean optimization to recover area, power and to fix setup and hold timing violations.
Using simulation and debugging tools for RTL and Netlist validation.
Using GPU architectures to understand dataflow and steer synthesis and optimizations techniques.

Responsibilities

Optimizing and Implementing designs for chips in hardware devices.
Designing synthesis to convert functional Register Transfer Level code to digital logic gates in physical chip design.
Performing Static timing analysis and constraint development to ensure that the physical design meets timing requirements.
Working on Power integrity checks to ensure that the various power domains and their interfaces are complete.
Working on Signoff checks to develop and maintain flows that help verify the overall quality of the chip designs.
Engineering Change Order implementations to meet the overall functionality and timing closure of the design.
Working with the CAD team and tool vendors to identify and quickly resolve any flow or integration issues.
Creating innovative flows and processes to support new chip designs.
Performing Lint checks, to ensure the overall quality of Register Transfer Level code meets the guidelines.
Optimizing logic designs to achieve low power, low area, high performance and timing goals.