FE Engineering

Apple•Cupertino, CA

6d•$148,987 - $194,700•Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Work on timing closure aspect of ASIC chips in deep sub-micron process. Responsible for SoC (System-on-Chip) design effort interfacing with all disciplines. Develop and enhance timing constraints for a complex, multi-clock and multi-voltage SoC. Develop timing constraint and coverage analysis scripts and checks. Develop and enhance timing related scripts for critical path analysis, and various hard macro interfaces. Develop full chip as well as block level constraints for multiple timing modes. Work on timing closure of I/O interfaces. Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation). Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints. Work on Apple SoC chips in deep sub-micron technologies targeted for high end mobile applications. Work closely with various cross functional teams on resolving complex timing issues for major building blocks of complex SoCs. 40 hours/week.

Requirements

Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field.
Digital Electronic circuits that include Combinational as well as Sequential logic gates to identify critical timing paths, analyzing setup/hold violations and interpreting timing relationships precisely.
Understanding Analog Electronic circuits and real chip timing dependency on analog effects such as voltage drops, temperature effects, parasitic resistance and capacitance, and signal integrity, e.g. crosstalk, noise.
Utilizing Computer Systems and Computer Architecture to have awareness of pipeline structure, memory hierarchy, and clock domains help in STA (Static Timing Analysis) modeling by providing a clear view of SoC (System-On-Chip) interconnections.
Utilizing Finite State Machine design to recognize FSM patterns helps define correct design constraints rules such as multi-cycle paths or false path exceptions
Using RTL (Register Transfer Level) programming languages such as Verilog or VHDL to debug synthesized netlists and timing violations by correlating them to RTL code.
Using computer programming languages such as C/C++ or Python for automating parsing of reports, analyzing slack distributions, and generating or refining constraints.

Responsibilities

Work on timing closure aspect of ASIC chips in deep sub-micron process.
Responsible for SoC (System-on-Chip) design effort interfacing with all disciplines.
Develop and enhance timing constraints for a complex, multi-clock and multi-voltage SoC.
Develop timing constraint and coverage analysis scripts and checks.
Develop and enhance timing related scripts for critical path analysis, and various hard macro interfaces.
Develop full chip as well as block level constraints for multiple timing modes.
Work on timing closure of I/O interfaces.
Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation).
Develop and maintain methodology and flows related to timing verification and closure.
Generation of block and full chip timing constraints.
Work on Apple SoC chips in deep sub-micron technologies targeted for high end mobile applications.
Work closely with various cross functional teams on resolving complex timing issues for major building blocks of complex SoCs.