Etch Engineer - Process Owner

Samsung • Taylor, TX

4d • Onsite

About The Position

Samsung Austin Semiconductor is hiring Etch Engineers - Process Owners to develop and optimize front-end-of-line (FEOL) and back-end-of-line (BEOL) plasma etch processes for emerging Gate-All-Around (GAA) architectures, including the 2 nm node, and mature nodes including 14 nm, 17 nm, and 28 nm FinFET. The role supports semiconductor manufacturing for automotive electronics, memory devices, RF technologies, and advanced display applications.

The position includes implementing and sustaining advanced process control, monitoring and investigating process performance and yield, qualifying and integrating etch equipment, and supporting process matching and technology transfers across global manufacturing sites. It also supports factory ramp-up, post-maintenance qualification, process optimization, defect reduction, and operational efficiency through collaboration with equipment engineering, process integration, metrology, and yield enhancement teams.

The role uses statistical and experimental methods and analytics tools to optimize processes and investigate defects, and applies semiconductor characterization techniques for failure analysis. This is a full-time, on-site position. The stated base salary range is $102,230 to $122,230. Compensation also includes a benefits package and may include company incentive compensation programs.

Requirements

• Bachelor’s degree in Chemical Engineering, Materials Science Engineering, Electrical Engineering, Semiconductor Engineering, or a closely related engineering discipline.
• At least 24 months of experience in the job offered or in a semiconductor plasma etch process engineering role within an advanced-node semiconductor manufacturing environment.
• At least 24 months of experience developing and sustaining BEOL and FEOL dry plasma etch processes.
• At least 24 months of experience in semiconductor manufacturing using FinFET and/or GAA technologies, including Nanosheet 3D transistor technology and Copper to Copper Hybrid Bonding.
• At least 24 months of experience with SPC, FDC, APC, and statistical yield analysis methodologies for detecting, correcting, and optimizing manufacturing processes.
• At least 24 months of experience authoring critical SOPs for novel etch processes.
• At least 24 months of experience supporting new product introduction through etch recipe and tool-spread optimization and implementation of APC processes such as Feed Forward APC.
• At least 24 months of experience with semiconductor tool qualification and process matching to establish matching process baselines and hardware-to-hardware reproducibility.
• At least 24 months of experience with root-cause analysis for yield excursions and defect reduction.
• At least 24 months of experience optimizing semiconductor processes using DOE methodologies.
• At least 24 months of experience with semiconductor metrology and characterization, including SEM and EDX analysis.
• At least 24 months of experience using statistical analytics software such as Spotfire, JMP, Minitab, or Python for yield optimization, process optimization, and equipment-failure detection.
• At least 24 months of experience supporting high-volume manufacturing and factory ramps.

Responsibilities

• Develop and optimize FEOL and BEOL plasma etch processes for emerging GAA architectures and mature semiconductor technology nodes.
• Implement and sustain Advanced Process Control (APC) methodologies, including feed-forward process control for trench etch and via-height optimization.
• Perform SPC/FDC monitoring, statistical yield analysis, and root-cause investigations into plasma etch excursions, interlocks, and OCAP events.
• Qualify and integrate heterogeneous etch tool platforms and cross-platform etch equipment for production deployment.
• Conduct process matching and technology transfer activities across global semiconductor manufacturing sites.
• Support factory ramp-up through tool qualification planning, capacity optimization, and throughput improvement initiatives.
• Develop monitoring plans for post-preventive-maintenance defect detection and production wafer qualification.
• Collaborate with equipment engineering, process integration, metrology, and yield enhancement teams to improve process stability and manufacturing efficiency.
• Use DOE methodologies and statistical analytics platforms to optimize processes and reduce defects.
• Perform failure analysis and material characterization using SEM, EDX, spectroscopy, and related techniques.
• Support semiconductor manufacturing for automotive electronics, memory devices, RF technologies, and advanced display applications.
• Participate in cost-reduction and risk-assessment initiatives involving process hardware qualification and fab operational efficiency.
• Author critical standard operating procedures for novel etch processes.
• Facilitate new product introductions by optimizing etch recipes and tool spread and implementing novel APC processes.
• Support high-volume manufacturing and factory ramp-up to transition semiconductor designs into mass-produced products.

Benefits

• Medical, dental, and vision insurance
• Life insurance
• 401(k) matching with immediate vesting
• Onsite cafés
• Onsite workout facilities
• Paid maternity leave
• Paid paternity leave
• Paid time off, two personal holidays, and 10 regular holidays
• Wellness incentives
• Eligible full-time employees may receive MBO bonuses based on company, division, and individual performance
• Competitive benefits package
• Potential participation in company incentive compensation programs based on organizational and individual performance

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level