Engineering Intern - Design-for-Test (Spring 2027 Co-Op)

Rivian•Palo Alto, CA

40d•Onsite

About The Position

Rivian internships are experiences optimized for student candidates. To be eligible, you must be an undergraduate or graduate student in an accredited program during the internship term with an expected graduation date between December 2027 and 2029. Rivian's Internship Program requires active student enrollment. Information regarding your expected degree completion date is collected solely to verify eligibility and determine your availability for future full-time opportunities. Rivian is an equal opportunity employer and does not use graduation dates to determine the age of applicants or as a basis for discriminatory hiring decisions. If you are not pursuing a degree, please see our full time positions on our Rivian careers site. Note that if your university has specific requirements for internship programs, it is your responsibility to fulfill those requirements. Our Spring Co-op program runs from Jan-Aug 2027. In order to be considered for this role, you must be available to work onsite, full time (40 hours per week), for the entire duration. If you're unable to work during the spring semester, please instead apply to our Summer Internship Program. No Visa Sponsorship Develop Design-for-Test (DFT) Verification Framework for different DFT Features(Memory Test, Logic Test, Analog IP) using AI , generation of verification summary and dashboard results for block level and chip level. In this role you will developing Design for Test Methodology for NextGen Rivian Autonomy Processor.

Requirements

Must be currently pursuing a bachelors, masters, or PhD degree at an accredited university. Masters preferred.
Actively pursuing a degree or one closely related in Electrical Engineering, Computer Engineering, or Computer Science
Digital Logic design
RTL Coding like Verilog /VHDL/System Verilog
TCL/Python Scripting
Design/Verification knowledge.
Familiar in using EDA tools

Responsibilities

Creating Block level, Chip Level Verification setup using Post -DFT RTL/Netlist.
Run simulation using the test list or patterns.
Memory Built-in Self test[MBIST] Verification Report Generation
Analog IP(PVT, Serdes PHY, DDR PHY) Tests Verification report generation
Scan/ATPG Verification, Test Coverage Report Generation.