Electrical Design Engineer (Compute Test, Arden Hills, MN)

Teradyne•New Brighton, MN

2d•$114,000 - $182,500

About The Position

Teradyne's Semiconductor Test Division is seeking a Hardware Engineer – Signal Integrity to join the Digital Instrument hardware team in Arden Hills, Minnesota. The team develops digital instruments that test advanced semiconductor devices, with signals ranging from kHz-rate control buses to tens-of-GHz serial links. The role owns signal integrity (SI) and power integrity (PI) for printed circuit board assemblies (PCBAs), from pre-layout modeling and simulation through lab correlation and production release, and designs selected functional circuit blocks. The engineer collaborates with Hardware, Firmware, Software, Mechanical, and Test engineers to translate instrument requirements into design guidelines and constraints, identify SI/PI risks before board re-spins, and solve problems on new and existing designs.

Requirements

Bachelor of Science in Electrical Engineering or a related field and at least 5 years of relevant design, simulation, and model-creation experience in a product development environment; or a Master of Science in Electrical Engineering or a related field and at least 3 years of such experience.
Relevant experience must include SI/PI simulation and model creation, PCB stack-up and layout review, schematic capture and review, and electronic lab correlation measurement.
Strong working knowledge of signal integrity and power integrity for low-speed through multi-gigabit interfaces.
Strong proficiency with SI/PI and circuit simulation tools and scripting, such as Cadence Sigrity/Clarity 3D, Ansys SIwave/HFSS, SPICE, and Python.
Hands-on experience with high-speed channel analysis, including S-parameters, IBIS models, and jitter/eye analysis.
Experience with schematic and layout CAD packages, such as Cadence Allegro/OrCAD, Altium, or Siemens Xpedition.
Working knowledge of board-level circuit design, such as clocking, termination, and power sequencing, and schematic review.
Proficiency with high-speed lab measurement equipment, such as VNA, TDR/TDT, sampling oscilloscopes, and BERT.
Excellent verbal, written, and presentation communication skills, including communication with geographically dispersed teams.
Ability to work independently and collaborate effectively in team environments.
Must be local to the position location; relocation is not provided.
The position is not eligible for visa sponsorship.

Nice To Haves

2D/3D model extraction and Gerber/ODB++ artwork review.
PAM4 channel analysis and S-parameter de-embedding.
Board-level digital and mixed-signal circuit design, including FPGA-based designs, clocking, and ADC/DAC.
Familiarity with relevant industry standards, such as IPC and JEDEC.
ATE, DIB/loadboard, or probe-card SI experience.

Responsibilities

Conduct signal integrity and power integrity (SI/PI) simulation and evaluation.
Own pre- and post-layout SI simulation for interfaces including I2C/SPI/JTAG, DDR, Ethernet, PCIe Gen 1–7 (up to 128 GT/s), and proprietary links.
Evaluate NRZ and PAM4 channel loss budgets, crosstalk, jitter/eye, impedance, and connector, via, and BGA breakout optimization.
Execute power integrity evaluation, including power distribution network (PDN) impedance, IR drop, and decoupling selection.
Model and correlate the full tester-to-DUT signal path—including instrument, interconnect, DIB/loadboard, and socket—against VNA, TDR, and BERT/sampling-scope measurements.
Own SI/PI work for PCBAs from pre-layout modeling and simulation through lab correlation and production release.
Design selected functional circuit blocks.
Work with Hardware, Firmware, Software, Mechanical, and Test engineers to translate instrument requirements into design guidelines and constraints, identify SI/PI risks, and solve problems on new and existing designs.