DSP Engineer

ThinKom Solutions•Hawthorne, CA

5d•Onsite

About The Position

Join Thinkom Solutions as a DSP Engineer specializing in coherent RF signal combining and beam forming. We are seeking a technical lead to architect, design, and develop robust FPGA-based solutions within a C++/Xilinx HLS environment. If you excel at creating and optimizing high-bandwidth RF architectures and turning theoretical DSP into efficient silicon reality, we want to hear from you.

Requirements

MS or BS in Electrical Engineering, Computer Engineering, or related field, or related engineering field.
5+ years of professional experience in FPGA development, specifically in signal processing and high-speed I/O.
Proven expertise with Xilinx HLS (Vivado / Vitis) and writing performance-critical C++ for FPGA synthesis.
Hands-on experience with coherent combining, beamforming, or similar multi-channel synchronization techniques.
Strong knowledge of VITA 49, including metadata handling and packet-based transport of digitized signals.
Proficiency in VHDL/Verilog and FPGA design methodologies.
Experience with Vivado Design Suite and Xilinx SDK.
Familiarity with high-bandwidth networking protocols (Ethernet up to 100Gb, PCIe, or similar).
Solid grasp of digital signal processing fundamentals (filters, FFTs, channelization, interference cancellation).
Proficiency in FPGA development flows (Vivado, ModelSim, or similar) and lab debugging (ILAs, scopes).
Excellent communication and collaboration skills.
Must be eligible to obtain and hold a US DoD Security Clearance in support of US Government contracts/subcontracts.
Willing to be in office 5-days/week.

Nice To Haves

Knowledge of Software-Defined Radio (SDR) is a plus.
Experience with Xilinx RFSoC is a plus.
Advanced degree (MSEE/PhD) with a focus on DSP, RF Communications, or FPGA acceleration preferred.
Experience with additional standards/protocols relevant to software-defined radio or phased-array systems preferred.
Familiarity with scripting languages (Python, TCL) for automation and testing is highly desirable.
Track record of publishing or patenting innovations in signal processing or hardware acceleration highly desirable.

Responsibilities

Develop coherent combining and beamforming modules using C++ and Xilinx HLS, ensuring precise phase alignment and time delay across multiple channels.
Requirements capturing, design definition & implementation of VHDL detailed designs.
Implement VITA 49-compliant data packetization for high-speed IF or RF data distribution.
Design and fine-tune DSP blocks (e.g., FFT, filtering, NCO, cross-correlation) to meet stringent real-time and resource utilization requirements.
Work closely with cross-functional teams to ensure signal integrity and minimize latency in large-scale, multi-channel systems.
Use Vivado (or Vitis) for synthesis, simulation, timing closure, and debug.
Create testbenches in C++/System Verilog/Python to validate functional correctness and phase coherence across all channels.
Provide guidance to junior engineers, reviewing design approaches and ensuring best practices for coherent signal processing.
Collaborate with firmware, software, and hardware teams to define project requirements and deliver high-quality solutions on schedule.
Other duties as assigned.