Distinguished Engineer - Digital Design

Marvell Technology•San Diego, CA

23h•$212,200 - $314,020

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Join Marvell's Custom Compute Solutions Business Unit (CCSBU) as we establish our design presence in San Diego's thriving semiconductor ecosystem. This team will be responsible for delivering high‑quality customer silicon for advanced AI, XPU, and XPU‑Attach programs. By partnering closely with customers and internal stakeholders, the design center will enable Marvell’s most strategic and financially significant custom SoC initiatives, delivering differentiated solutions that reinforce Marvell’s position as a trusted partner for next‑generation compute platforms. This is a rare technical leadership opportunity - you'll help shape design strategy from the ground up and build a world-class team as part of our strategic expansion into Southern California. You're not joining an established local team - you're building one. You'll define the culture, establish the methodology, and shape the technical DNA of Marvell's San Diego design organization.

Requirements

Fluent in SystemVerilog RTL coding techniques.
Experience in high speed, multiple clock domain designs
Expertise in PCIe, CXL protocols
Familiar with modern SoC architectures and various interface technologies such as AXI, DDR, Ethernet, PCIe.
Experience in micro-architecture of complex custom/ASIC products involving Chip I/O, shared memory, and embedded processors
RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.
Ability to create SVA assertions and apply formal verification concepts and tools
Ability to come up with creative and innovative solutions, and display technical leadership from within a team of engineers
Excellent verbal and written communication
Discipline and rigor in documentation
Ability to work efficiently and influentially with team members across multiple sites
Enthusiastic about exploring and applying new methods, tools, and process efficiency to ASIC design flow

Nice To Haves

Experience in designing high speed (>1 GHz)/high-performance embedded processor SOC products is a plus.
Experience in implementation/timing closure for high speed design.
Hands-on experience for all aspects of chip-development process with proficiency in front-end design tools and methodologies.
Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is desirable.

Responsibilities

Shape the micro-architecture of the chip
Write specifications and define micro-architecture of the design
Implement designs using low-power RTL coding techniques
Collaborate with the verification team on the verification test plan, coverage analysis, and full-chip simulation plus debug
Write SVA assertions for dynamic simulation and apply them in formal verification
Prepare and present design reviews
Work with the physical design team in aiding the implementation of the functional blocks
Interact with the project manager to scope and assign tasks
Provide reasonable and accurate schedule estimates and follow through to meet them in spite of surprises
Proactively communicate challenges and provide contingency plan recommendations to management
Work with multiple design centers and design groups to shape future methodology
Support the post silicon team to bring up silicon in the lab
Work with the software team to ensure product meets customer use cases
Provide expert product support in post-silicon debug environments