Director - Ultra Low-latency Trading System Architect

RBC•New York, NY

4d•$210,000 - $275,000•Onsite

About The Position

RBC is seeking a Senior Technologist to lead the design and implementation of an ultra-low-latency electronic trading platform targeting microsecond and sub-microsecond latencies. The role spans protocol design, distributed systems, market data infrastructure, hardware acceleration, and operational resilience. The successful candidate will own technical strategy, establish engineering standards, and ensure the platform meets demanding latency targets while maintaining deterministic failover and production reliability. The Director will architect the system’s messaging and sequencing layers, market data ingestion, Direct Market Access (DMA) engine, normalized venue integration, risk enforcement, replication and recovery, and network infrastructure. The role includes evaluating FPGA acceleration and kernel-bypass technologies, optimizing operating-system and hardware configuration, and designing observability that measures system performance without adding latency or jitter. The platform is intended to support deterministic replay and recovery while meeting demanding order-processing and risk-enforcement targets. This is a salaried, full-time, regular position on RBC’s Capital Markets platform, based at Brookfield Place in New York. The listed work schedule is 40 hours per week. The expected salary range is $210,000–$275,000, depending on factors including experience, skills, registration status, market conditions, and business needs. Total compensation may also include a discretionary bonus and benefits, including a 401(k) program with company matching contributions, health, dental, vision, life and disability insurance, and paid time off.

Requirements

Expertise in ultra-low-latency systems engineering.
Expertise in distributed systems and deterministic computing.
Expertise in financial markets and high-frequency trading.
Expertise in message protocol and serialization design.
Expertise in kernel-level systems programming and operating-system optimization.
Expertise in performance engineering and profiling at scale.
Expertise in systems programming and production operations.

Nice To Haves

Experience with market-data feed handlers and direct exchange connectivity.
A track record of building end-to-end ultra-low-latency systems from architecture through production.
Familiarity with order-entry normalization frameworks.
Experience with kernel-bypass networking such as DPDK or Open Onload.
Experience designing systems that pass regulatory audits or compliance reviews.
Familiarity with colocation, direct exchange connectivity, or private-fiber leases.
Familiarity with trading-specific FPGA solutions such as Exegy, Arista switches, Efinix SmartNIC, or similar.
Familiarity with global regulatory regimes.

Responsibilities

Lead the design and implementation of an ultra-low-latency electronic trading platform.
Own the technical strategy, establish engineering standards, and ensure latency targets, deterministic failover, and production reliability.
Design the foundational messaging layer and evaluate FIX and Simple Binary Encoding for internal components.
Evaluate and architect FPGA acceleration for latency-critical functions, including market data parsing, order matching, risk checks, and routing decisions; determine which components warrant FPGA implementation based on latency, throughput, and cost.
Work with FPGA and trading technology vendors, including Exegy and Redline, and establish FPGA trading components.
Architect kernel-bypass networking using technologies such as DPDK and Open Onload; design interrupt handling, packet batching, memory management, CPU affinity and isolation, CPU pinning, isolcpus configuration, and NUMA optimization.
Design a deterministic, replayable sequencer and event stream, including durability, sequence numbering, clock-skew handling, network-partition handling, replica synchronization, and stateless replica recovery.
Design low-latency market data ingestion, evaluating exchange multicast direct feeds, FPGA-based parsing, kernel-bypass software processing, and low-overhead data normalization.
Lead the design of the DMA engine for sub-ten-microsecond order processing, including concurrent market-data consumption, atomic order state management, failover, order lifecycle handling, and deterministic replay.
Design normalized order-entry abstractions and venue adapters for markets such as NYSE and NASDAQ, encapsulating venue-specific behaviors while minimizing latency overhead.
Design a risk-check framework for sub-microsecond enforcement, including client-level limits, market-access limits, pre-flight validation, FPGA versus software implementation, emergency bypass procedures, testability, and auditability.
Architect replica management, synchronization through sequencer replay, failover, consistency models, and recovery objectives measured in milliseconds or less.
Design latency-focused network topology, including colocation placement, proximity to exchanges and liquidity providers, minimizing network hops, and potential private-fiber leases.
Design low-overhead monitoring and observability using hardware performance counters, tracing, out-of-band monitoring, nanosecond-precision timing, and appropriate alert thresholds.
Identify and implement performance optimizations such as kernel bypass, CPU pinning, lock-free data structures, memory-layout optimization, NUMA awareness, cache-line alignment, SIMD, branch-prediction tuning, and custom CPU instructions where applicable.