Director - Ultra Low-latency Trading System Architect

Royal Bank of Canada•New York, NY

3d•$210,000 - $275,000•Onsite

About The Position

RBC is seeking a Senior Technologist to lead the design and implementation of an ultra-low-latency electronic trading platform targeting microsecond and sub-microsecond latencies. The role owns technical strategy, establishes engineering standards, and ensures the platform meets aggressive latency targets while maintaining deterministic failover and production reliability. The Director will architect messaging and protocol design, FPGA and hardware acceleration, kernel-bypass networking and operating-system optimization, deterministic sequencing and event streams, market-data ingestion, Direct Market Access and order management, normalized order entry and venue integrations, and risk enforcement. The position also leads replica management, deterministic recovery, network and colocation optimization, low-overhead monitoring and observability, and performance profiling and hardware tuning. The role is based at Brookfield Place, 200 Vesey Street, New York, and is a regular, salaried, full-time position with a 40-hour work week. The expected salary range is $210,000–$275,000, depending on factors including experience, skills, registration status, market conditions, and business needs. Total compensation may also include a discretionary bonus and benefits such as a 401(k) with company matching, health, dental, vision, life and disability insurance, and paid time off.

Requirements

Expertise in ultra-low-latency systems engineering.
Expertise in distributed systems and deterministic computing.
Expertise in financial markets and high-frequency trading.
Expertise in message protocol and serialization design.
Expertise in kernel-level systems programming and operating-system optimization.
Expertise in performance engineering and profiling at scale.
Expertise in systems programming and production operations.

Nice To Haves

Experience with market-data feed handlers and direct exchange connectivity.
A track record of building end-to-end ultra-low-latency systems from architecture through production.
Familiarity with order-entry normalization frameworks.
Experience with kernel-bypass networking such as DPDK or Open Onload.
Experience designing systems that pass regulatory audits or compliance reviews.
Familiarity with colocations, direct exchange connectivity, or private fiber leases.
Familiarity with trading-specific FPGA solutions such as Exegy, Arista switches, Efinix SmartNIC, or similar.
Familiarity with global regulatory regimes.

Responsibilities

Design the foundational messaging layer and evaluate protocol trade-offs, including FIX and Simple Binary Encoding for internal components.
Evaluate and architect FPGA-based acceleration for latency-critical paths, including market-data parsing, order matching, risk checks, and routing decisions; define which components merit FPGA implementation and work with vendors to establish FPGA trading components.
Architect kernel-bypass networking using DPDK, Open Onload, or similar technologies, including interrupt handling, packet batching, memory management, CPU affinity and isolation, and NUMA optimization.
Architect a deterministic, replayable sequencer and event stream; define durability, replication, sequence numbering, clock-skew and partition handling, and replica synchronization to enable stateless recovery without bottlenecks.
Design market-data ingestion for microsecond-scale processing, evaluating direct exchange feeds, FPGA parsing, kernel-bypass software processing, and low-overhead normalization.
Lead design of the Direct Market Access engine for sub-ten-microsecond order processing, including concurrent market-data consumption, atomic order state, order lifecycle handling, deterministic replay, and consistent failover.
Design normalized order-entry abstractions and venue adapters for multiple markets, encapsulating venue-specific differences while minimizing latency overhead.
Design a risk-check framework targeting sub-microsecond enforcement, covering client and market-access limits, pre-flight validation, software versus FPGA implementation, emergency bypass procedures, testing, and auditability.
Architect replica management, sequencer-based synchronization, and failover for DMA Engine replicas; define trading-appropriate consistency models and recovery time objectives.
Design latency-focused network topology, including colocation placement, proximity to exchange feeds and liquidity providers, minimized network hops, and potential private fiber leases.
Design low-overhead monitoring and operational controls, including hardware performance counters, tracing, out-of-band monitoring, nanosecond-precision latency measurement, and alert thresholds.
Identify and implement performance optimizations such as kernel bypass, CPU pinning, lock-free data structures, memory-layout optimization, NUMA awareness, cache-line alignment, SIMD, branch-prediction tuning, and custom CPU instructions where applicable.
Own the technical strategy, establish engineering standards, and ensure latency targets, deterministic failover, and production reliability.