Director Systems NPI Engineering

d-Matrix•Santa Clara, CA

5d•$150,000 - $300,000•Hybrid

About The Position

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI. About d-Matrix d-Matrix builds AI inference compute platforms purpose-built for generative AI at scale. Our digital in-memory compute architecture is shipping in the Corsair PCIe accelerator, with multi-chip-module accelerator cards and scale-up rack platforms on the near-term roadmap. We work directly with hyperscalers and ecosystem leaders to bring breakthrough inference economics to production. The Role We're hiring a Director, Systems NPI Engineering to lead the team that takes our next generation of AI accelerator hardware from concept through mass production. You'll own cross-functional execution across board, tray, thermal, power delivery, SI/PI, FW bring-up, and validation — on spec, on cost, and on schedule — reporting to the Sr. Director, Systems Engineering. This is a build role. You'll inherit an in-flight portfolio of accelerator cards, an AI-fabric NIC, and scale-up rack programs, and you'll shape the NPI engineering organization that delivers them.

Requirements

15+ years in systems / hardware engineering for compute or networking platforms, with 5+ years leading multi-team NPI execution at director or senior engineering-management level.
End-to-end ownership of at least two NPI programs taken from Concept through MP at the card or rack level.
Deep working knowledge across the systems stack: board design, SI/PI, power delivery, thermal / mechanical, FW bring-up, validation, manufacturing readiness.
Experience delivering high-power, high-density systems (multi-hundred-watt accelerators or dense rack-scale platforms) into hyperscaler or HPC environments.
Track record leading technical partner engagement (silicon, interconnect, ASIC, ODM) and hyperscaler customer interaction.
Demonstrated success building and scaling NPI engineering organizations.
BS in Electrical Engineering, Computer Engineering, or related discipline.

Nice To Haves

MCM / chiplet / advanced packaging systems integration experience.
Hands-on with scale-up coherent / chip-to-chip interconnects, CXL, PCIe Gen 5/6/7, or scale-out fabric (Ethernet / InfiniBand).
Liquid-cooled rack-scale systems delivered to MP (cold plate, manifold, CDU integration).
Prior role taking AI accelerator silicon from first samples to volume production in a customer-deployed platform.
MS or PhD in Electrical Engineering / Computer Engineering.

Responsibilities

Drive end-to-end NPI execution from Concept through EVT, DVT, PVT, and MP across multiple concurrent programs.
Own systems-level architectural sign-off and engineering change control for cards, trays, and rack platforms.
Build and lead the NPI engineering org — board / system HW design, FPGA design, NPI lab operations — and partner with matrixed function leads in SI/PI, package, thermal, and mechanical.
Lead technical engagement with silicon partners, interconnect / IP providers, networking-ASIC suppliers, and tier-1 ODMs.
Support hyperscaler customer engagements at the technical layer — design wins, PoCs, and integration deep-dives.
Define the validation matrix per program and drive risk burn-down through a clean hand-off to production ramp.