Director, Package Design Engineering

Renesas Electronics•Phoenix, AZ

3d•Onsite

About The Position

This role focuses on the design and development of package and interconnect methods for Renesas’s AI/Datacenter Infrastructure Power packaging needs, specifically for Smart Power Stages, Vertical Power Stages, Power Modules & Discrete FET packages. The scope includes Wide Bandgap (WBG) development, such as SiC & GaN, along with DBC, AMB substrates, and advanced interconnect technologies. Responsibilities include package technology development, R&D, global OSAT management for new package development and product qualification, technology roadmap definition, R&D budget management, and customer adoption programs. The position also involves benchmarking, selecting, and qualifying materials, processes, and subcontractors, developing and optimizing processes, establishing process specifications, and ensuring smooth transition into production. The role requires developing and maintaining technical expertise in power SiP/modules, wafer level packaging, and flip chip interconnects, participating in packaging roadmap development, and addressing customer complaints.

Requirements

Doctorate/Masters / Bachelor’s Degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.
15 to 20 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip packaging
Strong understanding of power SiP/modules, wafer level/flip-chip packaging methods, assembly process knowledge, qualification methods, SPC and statistical analysis software.
Strong interpersonal and communication skills.
Strong analytical and presentation skills.

Nice To Haves

Knowledge of wafer level, flip-chip, multi-chip module and power devices will be a plus.
Knowledge of wire-bonding & multi-chip module technologies a plus.

Responsibilities

Package Technology Development/NPI, R&D, Global OSAT management for new Package Development/Product qualification, Technology Roadmap definition, R&D budget management & customer adoption programs.
Focus on design and development of package and interconnect methods for Renesas’s AI/Datacenter Infrastructure Power packaging needs especially Smart Power Stages, Vertical Power Stages, Power Modules & Discrete FET packages. Scope also involves WBG (Ie. SiC & GaN) development along with DBC, AMB substrates and advanced interconnect technologies.
Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).
Work with OSAT/CM to develop, run DOE to optimize processes and establish process spec.
Work with Product groups and Reliability team, qualify new packages and processes within required time frame.
Resolve all process integration issues by ensuring all window checks are done on critical process steps.
Establish production controls and monitors to ensure there is no room for quality incidents.
Ensure smooth transition into production & implement ramp up monitor.
Work with OSAT/CM to monitor and resolve process issues early in the production phase to ensure only parts with superior quality shipped to customer.
Develop and maintain technical expertise on advances and innovations in power SiP/modules, wafer level packaging & flip chip interconnects.
Participate in packaging roadmap development & focus on execution.
Address internal and external customer complaints working with peers of Marketing, Product groups, Quality and Operations organization to satisfy growth in businesses.
Establish & maintain package design rules.