Director, Package Design Engineering

Renesas Electronics•San Jose, CA

2d•Onsite

About The Position

Renesas is seeking a Director, Package Design Engineering to lead package technology development, R&D, and global OSAT management for new package development and product qualification. This role involves defining the technology roadmap, managing the R&D budget, and driving customer adoption programs. The primary focus will be on the design and development of package and interconnect methods for Renesas’s AI/Datacenter Infrastructure Power packaging needs, specifically for Smart Power Stages, Vertical Power Stages, Power Modules, and Discrete FET packages. The scope also includes WBG (SiC & GaN) development, DBC, AMB substrates, and advanced interconnect technologies. The position requires a strong understanding of wafer level, flip-chip, multi-chip module, and power device packaging. Responsibilities include benchmarking, selecting, and qualifying materials, processes, and subcontractors (OSAT) or contract manufacturers (CM). The role involves working with OSAT/CM to develop and optimize processes, establish process specifications, and collaborate with Product groups and the Reliability team for new package and process qualification. Ensuring smooth transition into production, implementing ramp-up monitors, and resolving process integration issues are critical. The Director will also establish production controls, monitor and resolve early-stage production issues, and develop technical expertise in power SiP/modules, wafer level packaging, and flip-chip interconnects. Participation in packaging roadmap development and execution, addressing customer complaints, and establishing package design rules are also key aspects of this role.

Requirements

Doctorate/Masters / Bachelor’s Degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering
15 to 20 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip packaging
Strong understanding of power SiP/modules, wafer level/flip-chip packaging methods, assembly process knowledge, qualification methods, SPC and statistical analysis software
Strong interpersonal and communication skills
Strong analytical and presentation skills

Nice To Haves

Knowledge of wafer level, flip-chip, multi-chip module and power devices will be a plus
Knowledge of wire-bonding & multi-chip module technologies a plus

Responsibilities

Package Technology Development/NPI
R&D
Global OSAT management for new Package Development/Product qualification
Technology Roadmap definition
R&D budget management & customer adoption programs
Design and development of package and interconnect methods for Renesas’s AI/Datacenter Infrastructure Power packaging needs especially Smart Power Stages, Vertical Power Stages, Power Modules & Discrete FET packages
WBG (Ie. SiC & GaN) development along with DBC, AMB substrates and advanced interconnect technologies
Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM)
Work with OSAT/CM to develop, run DOE to optimize processes and establish process spec
Work with Product groups and Reliability team, qualify new packages and processes within required time frame
Resolve all process integration issues by ensuring all window checks are done on critical process steps
Establish production controls and monitors to ensure there is no room for quality incidents
Ensure smooth transition into production & implement ramp up monitor
Work with OSAT/CM to monitor and resolve process issues early in the production phase to ensure only parts with superior quality shipped to customer
Develop and maintain technical expertise on advances and innovations in power SiP/modules, wafer level packaging & flip chip interconnects
Participate in packaging roadmap development & focus on execution
Address internal and external customer complaints working with peers of Marketing, Product groups, Quality and Operations organization to satisfy growth in businesses
Establish & maintain package design rules