Director of ASIC Design Verification

SambaNova Systems • San Jose, CA

3d • Onsite

About The Position

SambaNova Systems is seeking a Director of ASIC Design Verification to lead end-to-end verification for their next generation of RDU chips. This role requires deep expertise in verification, not just management. The successful candidate will be the technical authority on methodology and the leader of the team, setting verification architecture and strategy for the full chip. Responsibilities include ensuring pre-silicon quality through tape-out, covering block, full-chip, and gate-level benches, performance verification, coverage closure, and emulation/FPGA prototyping. The role also involves supporting first silicon bring-up and debug in the lab. The Director will lead an experienced team of 8-10 engineers, including principal-level engineers, and will be responsible for the evolution of the verification environment, team growth, leveling, and maintaining technical standards as the silicon roadmap scales.

Requirements

• BS in EE, CS, or CE with 12+ years (or equivalent) of industry experience in ASIC design verification
• 5+ years managing design verification engineers, including hiring and performance management, with experience leading senior and principal-level engineers
• Track record of inheriting an established verification environment and evolving it with the team rather than replacing it wholesale
• Deep, current technical expertise in verification — able to own methodology, arbitrate testbench architecture, and personally lead debug on the hardest pre-silicon failures
• Full-cycle DV from planning through tape-out and into production silicon on at least one complex ASIC or large subsystem
• Deep hands-on foundation in SystemVerilog, SVA, Python, and industry verification methodologies such as UVM, OVM, or VMM
• Experience through silicon bring-up, including lab functional validation and debugging first-silicon issues to root cause
• Working knowledge of machine learning SoCs or microprocessors (CPU/GPU) and modern computer architecture
• Excellent communication skills and a track record of building consensus among stakeholders and team members

Nice To Haves

• MS or PhD in EECS with 15+ years of experience in ASIC design verification
• Multiple large-scale, high-impact chips led to silicon
• Scaling a DV team through a step change in headcount or chip complexity
• Owning or directing post-silicon functional validation in a lab environment
• Deep understanding of performance verification methodology
• High-performance interconnect protocols (PCIe, Ethernet) and memory subsystems
• Advanced TSMC nodes and modern multi-die or chiplet verification challenges
• Emulation and FPGA prototyping platforms
• Managing cross-site or distributed teams
• Fluency with Claude or other AI tools applied to verification and flow development

Responsibilities

• Own verification through tape-out
• Own pre-silicon functional and performance verification for SambaNova ASICs — quality, coverage closure, and on-time delivery to tape-out
• Define verification architecture, strategy, schedules, and DV environments for complex, high-performance machine learning ASICs
• Serve as the technical authority on verification: arbitrate testbench architecture, set coverage and sign-off criteria, and lead debug on the hardest failures
• Set and defend the DV schedule and own tape-out readiness sign-off, including the trade-off between coverage depth and time to silicon; report risk and readiness to executive staff with a clear point of view, not just a dashboard
• Carry ownership into first silicon — support lab functional validation and bring-up debug, feeding findings back into the pre-silicon environment
• Lead and grow the team
• Bring a strong point of view on methodology, and be willing to disagree with the team and with peers when the engineering case supports it
• Own the direction of an established verification environment — understand the reasoning behind it, then decide what to evolve and what to replace
• Lead, coach, and retain principal-level verification engineers; be accountable for their development and continued engagement
• Grow the team toward a multi-workstream org: own staffing requirements, leveling, interview loop design, closing senior candidates, and developing technical leads
• Own the methodology
• Own the DV methodology end to end — verification architecture, reuse strategy, and sign-off criteria
• Lead development of test benches, agents, checkers, and stimulus at block, full-chip, system, and gate level
• Drive pre-silicon debug and closure in both functionality and performance; own regression health and root-cause discipline
• Land new DV methodologies and processes, including AI-assisted verification workflows, to improve execution effectiveness and efficiency
• Direct emulation and FPGA prototyping strategy, and own third-party verification IP evaluation and EDA vendor relationships for DV tooling
• Partner with architecture, design, and software teams to settle requirements and drive DV planning
• Work with the compiler and runtime teams to map ML application flows into verification, so silicon is validated against real workloads
• Partner with hardware and systems teams on lab validation of first silicon, and represent DV in reviews with physical design, process and quality, and product

Benefits

• Equity
• 95% premium coverage for employee medical insurance
• 77% premium coverage for dependents
• Health Savings Account (HSA) with employer contribution
• Dental insurance
• Vision insurance
• Short/Long term Disability insurance
• Basic Life insurance
• Voluntary Life insurance
• AD&D insurance
• Flexible Spending Account (FSA) options (Health Care, Limited Purpose, and Dependent Care)
• Full subscription to Headspace
• Gympass+ membership with access to physical gyms
• One Medical membership
• Counseling services with an Employee Assistance Program

What This Job Offers

• Job Type: Full-time
• Career Level: Director