Digital Verification Engineer Prime (FEC)
About The Position
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute: At Ciena, we are at the forefront of the telecommunications industry, and our Wavelogic modem family of products plays a crucial role in our success. As a Senior Digital Verification Engineer, you will be an integral part of a team responsible for implementing innovative verification strategies in order to thoroughly simulate and validate functional blocks and subsystems for Ciena’s Forward Error Correction (FEC) IP. Reporting to the ASIC Senior Manager, you will collaborate with a team of Digital Design Engineers, Verification Engineers, and Architects to simulate and validate functional blocks and subsystems.
Requirements
- 10+ years of experience in verification.
- Minimum Bachelor's degree in Electrical, Computer or Software Engineering.
- Significant experience in using C/C++, System Verilog, UVM, SVA, and simulators from major vendors.
- Proven ability to determine comprehensive digital verification and coverage strategies.
- Proven ability to foster a culture of innovation and continuous improvement within the team via demonstrated leadership and communication capabilities.
- Strong decision-making skills with the ability to analyze complex situations, evaluate options and implement effective solutions to meet deliverables.
- Detail-oriented – Deliver on objectives through meticulous, thorough, and comprehensive work.
- Problem solver – Analyze and solve complex technical problems using engineering principles.
- Commitment to learning – Keep abreast of technology developments and are keen to share your knowledge with others.
Nice To Haves
- Experience with formal verification methods.
- Strong background in Forward Error Correction (FEC) and/or DSP.
- Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++.
- Proficiency in bug tracking using Jira and source code management and revision tracking using GIT.
- Previous experience leading a team.
- Previous experience mentoring.
Responsibilities
- Read and understand the FEC architecture and functional requirements specification document(s) and communicate and collaborate with FEC designers, DSP modelers, FEC verifiers, systems engineers and architects.
- Develop verification, functional coverage and formal verification test plans.
- Thoroughly validate one or more architectural FEC functional blocks using a combination of simulation, formal, and coverage methods.
- Create testbench environments and components, agents, scoreboard, and test scenarios using System Verilog UVM and C++.
- Perform coverage-driven verification, monitor regressions, and debug failures with the support of the function's designer.
- Provide status updates on verification progress on a regular basis and communicate risks as needed.
- Mentor and supervise junior verification engineers requiring robust understanding of team outputs to foster peers’ technical and professional growth.
Benefits
- medical
- dental
- vision plans
- participation in 401(K) (USA) & DCPP (Canada) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- company-paid holidays
- paid sick leave
- vacation time
- Paid Family Leave
- other leaves of absence
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What This Job Offers
Job Type
Full-time
Career Level
Senior
