Digital Design Engineer Prime (FEC)
About The Position
As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. How You Will Contribute: At Ciena, we are at the forefront of the telecommunications industry, and our Wavelogic modem family of products plays a crucial role in our success. As a Senior Digital Design Engineer, you will be an integral part of a team responsible for implementing industry standard and custom subsystems for Ciena’s Forward Error Correction (FEC) IP. Reporting to the ASIC Senior Manager, you will collaborate with a team of Digital Design Engineers, Verification Engineers, and Architects.
Requirements
- 10+ years of ASIC/FPGA design experience successfully delivering complex designs
- Minimum Bachelor's degree in Electrical or Computer Engineering
- Significant experience in using C/C++, System Verilog, synthesis, power analysis, SDC, STA, CDC and simulators from major vendors
- Experience with high level synthesis (HLS) tools and methodologies
- Proven ability to implement designs to timing closure
Nice To Haves
- Strong background in Forward Error Correction (FEC) and/or DSP
- Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++
- Design for low power
- Proficiency in bug tracking using Jira and source code management and revision tracking using GIT
- Previous experience leading a team
- Previous experience mentoring
Responsibilities
- Read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers DSP systems, and architects
- Produce an implementation specification document and have it reviewed by your team, verification, architects, analog designers if applicable
- Creation and integration of new and existing RTL and/or C source code, algorithms and functions
- Work independently, come up with detailed design specification for an IP subcomponent and take it through all stages of design
- Designer testing of your code as well as debugging of your code during simulation and regression verification
- Assist the verification team in determining coverage and provide design assertions and waivers as needed
- Creating timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews
- Report on status updates on a regular basis
- Work closely with our ASIC verification team in various stages of verification of our IP
- Mentor and supervise junior verification engineers requiring robust understanding of team outputs to foster peers’ technical and professional growth
- Excellent communication and interpersonal skills with demonstrated ability to convey complex technical concepts clearly and effectively influence stakeholders
Benefits
- medical
- dental
- vision plans
- participation in 401(K) (USA) & DCPP (Canada) with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- company-paid holidays
- paid sick leave
- vacation time
- Paid Family Leave
- other leaves of absence
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What This Job Offers
Job Type
Full-time
Career Level
Senior
