Digital Verification Engineer - New Grad

Ciena • Pittsford, NY

1d

About The Position

The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry. To further strengthen our team, we are looking for an enthusiastic digital verification engineer who will be involved in the verification of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a digital verification engineer will be to implement innovative verification strategies, in order to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products. As a digital verification engineer, you are expected to read and understand the functional requirements specification document(s) and communicate and collaborate with systems engineers and architects You are responsible for the complete and thorough validation of one or more functional blocks by using an appropriate combination of simulation, formal and coverage methods You are expected the create the verification, functional coverage and formal verification test plans You will be part of a team that is accountable for the creation of testbench environment and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable You will perform coverage driven verification, monitor regressions and debug resulting failures with the help of the function's designer You are expected to report on status updates on a regular basis

Requirements

• Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc or MEng/MSc level.
• Highly motivated self-starter, able to work independently, while being a team player.
• Ability to methodically solve complex technical problems.
• Excellent organization, written and oral (English) communication skills.
• Proficiency above the intermediate level with the use of System Verilog, SVA, and simulators from major vendors.
• Proven ability in determining appropriate and comprehensive digital verification and coverage strategies.

Responsibilities

• Implement innovative verification strategies to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products.
• Read and understand functional requirements specification documents.
• Communicate and collaborate with systems engineers and architects.
• Ensure complete and thorough validation of one or more functional blocks using simulation, formal, and coverage methods.
• Create verification, functional coverage, and formal verification test plans.
• Create testbench environments and/or components, agents, and scoreboards.
• Develop all test scenarios related to architectural functional blocks using System Verilog UVM and/or C.
• Perform coverage-driven verification.
• Monitor regressions and debug resulting failures.
• Report on status updates on a regular basis.

Benefits

• medical
• dental
• vision plans
• 401(K) (USA) & DCPP (Canada) with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company-paid holidays
• paid sick leave
• vacation time
• Paid Family Leave
• other leaves of absence

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level