Digital Design Verification Engineer | Precision ADC

Texas Instruments•Tucson, AZ

3d•$81,500 - $146,500•Onsite

About The Position

Texas Instruments' Precision ADC team is seeking a Design Verification Engineer to help verify cutting-edge signal chain solutions utilizing delta-sigma ADCs. You will work alongside world-class analog and mixed-signal designers developing some of the highest-precision data converters in the industry. This is a hands-on role with real ownership, where your verification work directly contributes to products trusted in medical, industrial, automotive and instrumentation applications worldwide. In this position, you will develop SystemVerilog/UVM testbenches to verify the digital logic, calibration algorithms, and mixed-signal interfaces of Signal chains involving high-resolution delta-sigma ADCs. Your responsibilities will include building constrained-random stimulus environments, writing functional coverage models and assertions, running regression campaigns, and triaging simulation failures in close collaboration with the RTL and analog design teams. This position involves routine collaboration with a highly talented team of analog and digital design engineers. You will participate in design and verification reviews, present findings, and grow your expertise in mixed-signal verification methodology. We value curiosity and a drive to learn - if you are eager to develop deep skills in UVM and analog/mixed-signal verification, this team will give you the environment to do so.

Requirements

Develop SystemVerilog/UVM testbenches
Verify digital logic, calibration algorithms, and mixed-signal interfaces of Signal chains involving high-resolution delta-sigma ADCs
Build constrained-random stimulus environments
Write functional coverage models and assertions
Run regression campaigns
Triage simulation failures
Collaborate with RTL and analog design teams
Participate in design and verification reviews
Present findings
Grow expertise in mixed-signal verification methodology
Curiosity and a drive to learn
Eager to develop deep skills in UVM and analog/mixed-signal verification

Responsibilities

Develop SystemVerilog/UVM testbenches to verify the digital logic, calibration algorithms, and mixed-signal interfaces of Signal chains involving high-resolution delta-sigma ADCs.
Build constrained-random stimulus environments.
Write functional coverage models and assertions.
Run regression campaigns.
Triage simulation failures in close collaboration with the RTL and analog design teams.
Participate in design and verification reviews.
Present findings.
Grow your expertise in mixed-signal verification methodology.