Digital Design/RTL/Microarchitecture

Redolent • Menlo Park, CA

6d • Onsite

About The Position

One of our direct clients is urgently looking for a Digital Design/RTL/Microarchitecture professional in Menlo Park, CA. This role involves the conversion of algorithms from C/C++ reference models to RTL, microarchitectural breakdown of algorithms into hardware implementations, and debugging and performance improvement of algorithmic pipelines.

Requirements

• BSEE/MSEE/BSCompE/MSCompE with at least 5 years of Verilog/SystemVerilog RTL experience
• Experience with AMBA / AXI busses
• Familiarity with Python3/Bash/Tcl scripting is a must
• Experience with fixed-point arithmetic

Nice To Haves

• BSEE/MSEE/BSCompE/MSCompE with at least 10 years of Verilog/SystemVerilog RTL experience
• Experience with video processing or graphics pipelines is a plus
• Experience with back-end implementation flows is a plus
• Experience with high-level synthesis - Mentor Catapult, Vivado HLS - is a plus
• Experienced with a full ASIC/SOC tape out from beginning to end
• Experience with floating-point arithmetic in addition to fixed-point arithmetic

Responsibilities

• Conversion of algorithms from a C/C++ reference model to RTL
• Microarchitectural breakdown of algorithms into hardware implementations
• Debugging and improving the performance of algorithmic pipelines

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level