Digital Design Engineer

Qorvo•Chandler, AZ

2d•Hybrid

About The Position

Qorvo supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. This position involves the Verilog design of digital control logic for mobile phone LNAs, TX controllers and switches. The role requires working with and/or having knowledge of design and timing closure using Cadence Innovus, RTL-to-GDS flow, area optimization, and DRC/LVS error resolution. It also includes digital synthesis using Cadence Genus or Synopsys Design Compiler, Verilog digital design and verification, understanding of verification test benches, clocking and auto-checking, performing verification on Verilog code using simulation tools, and Python scripting. Responsibilities also include the creation of test benches and verification through simulation using Xcelium, Verilog and Python automation, constraint creation and synthesis with Cadence Genus and Conformal, and physical design and timing closure with Cadence Innovus. Additionally, script automation development with Python is required to aid in the design of Qorvo’s mobile designs. The work arrangement is hybrid, with 3 days in the office and 2 days working from within a reasonable commuting distance from the office.

Requirements

Master’s degree in Electrical Engineering
6 months of experience, an internship, co-op, or 6 graduate credit hours involving knowledge of:
Design and timing closure (TCL layout setup script generation, setup/hold/width timing violation fixing) using Cadence Innovus
RTL-to-GDS flow, area optimization, and DRC/LVS error resolution
Digital synthesis using Cadence Genus or Synopsys Design Compiler and timing constraint generation in TCL
Verilog digital design and verification and understanding of Verilog/System Verilog syntax
Understanding of verification test benches, clocking and auto-checking
Performing verification on the Verilog code using simulation tools
Python scripting and other scripting languages

Responsibilities

Verilog design of digital control logic for mobile phone LNAs, TX controllers and switches.
Working with and/or having knowledge of design and timing closure (TCL layout setup script generation, setup/hold/width timing violation fixing) using Cadence Innovus.
RTL-to-GDS flow, area optimization, and DRC/LVS error resolution.
Digital synthesis using Cadence Genus or Synopsys Design Compiler and timing constraint generation in TCL.
Verilog digital design and verification and understanding of Verilog/System Verilog syntax.
Understanding of verification test benches, clocking and auto-checking.
Performing verification on the Verilog code using simulation tools.
Python scripting and other scripting languages.
Creation of test benches and verification through simulation of the above designs using Xcelium, Verilog and Python automation.
Constraint creation and synthesis of mobile phone digital circuit designs with Cadence Genus, Conformal.
Physical design and timing closure of mobile phone digital circuit designs with Cadence Innovus.
Script automation development with Python to aid in the design of Qorvo’s mobile designs.