Digital and Mixed Signal IC Design/DV Engineer

Texas Instruments • Tucson, AZ

2d

About The Position

We are seeking a highly motivated and versatile engineer to join our dynamic Current Sensing product line that develops cutting edge Shunt and Hall based mixed signal current sensing ICs. As a key member of our team, you will play a vital role in all phases of IC development, from architectural development, design, DV, tapeout and bring-up. This position offers a unique opportunity to develop expertise in both digital and mixed-signal domains.

Requirements

• At least 2 years of relevant experience
• A thorough understanding of digital logic design
• Familiarity with the Verilog, System Verilog, VHDL language and simulators
• Ability to solve problems using a systematic approach

Nice To Haves

• A good understanding of analog functionality and exposure to analog IC design methods.
• Understanding and knowledge of analog and digital design principles, including RTL, FSMs, GLS, timing, synchronization, and power domains, mixed-signal and digital verification flow and analog block modeling.
• Experience with timing verification using Gates+SDF, electrical PVT variation, and timing analysis across analog/digital boundaries
• Demonstrated strong analytical and problem solving skills
• Strong verbal and written communication skills
• Ability to work in teams and collaborate effectively with people in different functions
• Strong time management skills that enable on-time project delivery
• Demonstrated ability to build strong, influential relationships
• Ability to work effectively in a fast-paced and rapidly changing environment
• Ability to take the initiative and drive for results

Responsibilities

• Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route, scan pattern generation, and timing analysis.
• Develop and implement robust, scalable verification methodologies for mixed-signal ICs, including testbench creation and automation using DMS and AMS stimulus and checkers.
• Create comprehensive test plans, tests, and simulations at RTL and gate levels using SystemVerilog (SV), VHDL, and the UVM environments.
• Work closely with design and system teams to define Design for Verification (DFV) architectures, triage and resolve bugs, and ensure first-pass silicon success.
• Drive verification coverage to meet defined goals, track progress, and communicate status, issues, and risks effectively.
• Develop and contribute to the evolution of our DV strategy, tools, scripts and methodologies to improve quality, efficiency and automation.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed