DFx Methodology Architect

Advanced Micro Devices, IncSan Jose, CA
Onsite

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Our global team is growing, and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything.

Requirements

  • Strong analytical and problem-solving skills
  • Willing to learn and ready to take on problems
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice To Haves

  • RTL design, timing constraints and design methodologies
  • Design qualification – STA, RTL-DRC, CDC, RDC, Constraints checking
  • Programming experience – Perl, TCL, Python
  • Design verification – Verilog simulation, coverage analysis, assertions
  • Prior knowledge of Scan design, ATPG, Memory BIST, Repair and harvesting for yield are a plus

Responsibilities

  • Define constraints and dependencies for IPs based on block interfaces, power supply & configuration requirements
  • Address and improve efficiency of timing, PnR, DRC and integration methodologies for DFx IPs
  • Develop new IPs and methodologies, including process characterization IP (timing, defectivity etc.) for test-vehicles
  • Define DFx Architecture for AMD’s next generation monolithic and stacked SoC product families, including testability, debug, characterization, repair and yield
  • Work with functional IP teams on integration, analysis and qualification methodologies for a growing number of DFx IPs, tools and flows

Benefits

  • AMD benefits at a glance
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