ASIC DFx & Test Architect Lead
About The Position
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments.
Requirements
- Bachelor's on Electrical Engineering with 10+ years (or Master’s with 8+ years) of experience on ASIC hardware development
- Prior experience with ASIC DFx and test relevant standards, and techniques.
- Prior experience with silicon life cycle, including manufacturing screening and qualification
- Prior experience on ASIC components including high speed IO’s and their test + diagnosis solutions
Nice To Haves
- Prior experience on hardware design specifications and verification plan/matrix.
- Prior experience on RTL QA checks, including lint & CDC
Responsibilities
- Responsible for development of the comprehensive DFx & test solutions and architectures that support ATE screening, in-system test, debug and diagnostics needs of the design.
- Lead the RTL implementation from the architecture specifications and required RTL quality checks implementations.
- Work with the team on Innovative Hardware DFx & test strategy aspects for for leading edge technology nodes and packaging styles, driving re-usable test and debug methodologies and standards.
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- grants of Cisco restricted stock units
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year (non-exempt)
- flexible vacation time off program (exempt)
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- Optional 10 paid days per full calendar year to volunteer
- annual bonuses (non-sales roles)
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What This Job Offers
Job Type
Full-time
Career Level
Senior
