Lead ASIC Design Engineer

Broadcom•San Jose, CA

3d•$143,800 - $230,000

About The Position

We are seeking a hands-on Principal Digital Design Engineer to serve as the Chip Lead for our next-generation silicon projects. In this high-impact role, you will be the primary technical anchor responsible for the top-level architecture, microarchitecture, and full chip integration. You will guide a cross-disciplinary team spanning analog design, physical design, and verification, owning the design outcome end-to-end from early product definition to a successful foundry tape-out.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead.
Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles.
Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites).
Must have a proven history of successful, first-pass silicon tape-outs on modern process technologies.
Outstanding documentation and verbal communication skills; this role authors the authoritative architectural and design specifications for the entire project.
Must have legal authorization to work in the US.

Nice To Haves

Experience with mixed-signal or high-speed PHY-adjacent architectures (e.g., SerDes, PCIe, DDR, or custom interconnects).
Familiarity with DFT (Design for Test) planning, including scan insertion, ATPG planning, and boundary scan.
Proficiency in scripting (Python, Tcl, Perl) to automate and streamline front-end design flows.

Responsibilities

Serve as the central Chip Lead, defining top-level digital architecture, partitioning hard/soft IP blocks, and owning the complete integration lifecycle.
Act as the bridge between Logic Design, Physical Design (PD), Architecture, and Design Verification (DV) to ensure all PPA (Power, Performance, Area) targets are met.
Own and drive the final tape-out sign-off checklist, coordinating across all technical teams to ensure a clean handoff to the foundry.
Provide technical guidance, code reviews, and architectural mentorship to mid-level and junior engineers on the team.
Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs).
Drive top-level chip timing constraints (SDC), define the Clock Domain Crossing (CDC) strategy, and establish block-level timing budgets for the PD team.
Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).
Manage the integration of custom internal analog macros, mixed-signal blocks, and third-party soft/hard IP.
Collaborate with post-silicon validation and software teams during initial chip bring-up and lab debug phases.