Principal RTL Methodology Architect

Ericsson • Austin, TX

3d • Hybrid

About The Position

The Team is part of the Ericsson Silicon engineering unit, which develops state of the art ASIC's and FPGA's targeting the newest technology nodes for Ericsson's 5G telecommunication product portfolio. This department offers many opportunities for career growth and a large base of knowledge to learn from.

Principal-level Silicon Frontend Architect with deep expertise in RTL design methodology, reusable IP architectures, and RTL quality signoff frameworks for large-scale ASIC and SoC development. Extensive experience defining scalable frontend design methodologies used across global engineering organizations to improve RTL quality, reuse, and development efficiency. Combines methodology leadership with hands-on RTL execution, actively contributing to RTL microarchitecture and design implementation while developing flows and infrastructure that enable high-quality silicon delivery. Proven ability to drive lint-first RTL development, IP reuse strategies, and automated frontend quality frameworks using industry tools such as SpyGlass and VC-based static analysis flows.

Requirements

• Deep expertise in SystemVerilog/Verilog RTL design, microarchitecture definition, and implementation for complex ASIC and SoC designs.
• Strong experience in high-performance block design, subsystem integration, and scalable RTL architecture across IP and SoC levels.
• Proven leadership in defining and deploying enterprise-scale RTL design methodologies and frontend CAD architectures.
• Expert in lint-first RTL development methodologies using SpyGlass and Synopsys VC SpyGlass / VC Lint for RTL quality signoff.
• Extensive knowledge of structural RTL validation, CDC analysis, and static quality gates for pre-silicon design signoff.
• Strong background in IP reuse architecture, including reusable RTL frameworks, standardized interfaces, and multi-program reuse strategies.
• Experience in low-power RTL design methodologies, including UPF-aware design, power domains, isolation, and retention strategies.
• Proficiency in frontend EDA tools including RTL simulators (VCS, Xcelium, Questa), linting, CDC, and synthesis integration flows.
• Strong expertise in automation and infrastructure development using Python, scripting, CI/CD pipelines, and design quality dashboards.
• Strong interest in AI-driven silicon design methodologies, with focus on applying AI/ML to improve RTL design productivity, intelligent linting, design space exploration, and next-generation frontend automation.
• BS/MS, Electrical Engineering, Computer Science or similar with 10+ years of experience.

Nice To Haves

• Strong interest in Artificial Intelligence and its transformative impact on silicon design, with a focus on applying AI/ML techniques to: enhance RTL design productivity and code generation, enable intelligent linting and static analysis, optimize design space exploration and microarchitecture decisions, improve automation of frontend design and verification workflows.
• Actively exploring how AI-driven methodologies can redefine traditional silicon development flows, enabling higher design efficiency, faster convergence, and improved silicon quality at scale.

Responsibilities

• Lead architecture, development, and deployment of RTL design methodologies and frontend design flows across IP, subsystem, and SoC programs.
• Define and enforce RTL quality signoff frameworks, including lint, CDC, and static analysis integrated into CI-driven development flows.
• Drive lint-first design adoption and establish standardized RTL coding guidelines and quality metrics across engineering teams.
• Architect and scale reusable IP platforms and configurable RTL frameworks to enable efficient multi-program silicon development.
• Develop and optimize frontend design flows integrating static analysis, simulation, and synthesis readiness checks.
• Maintain ~50% hands-on RTL design involvement, contributing to microarchitecture development and critical silicon blocks.
• Build and deploy automation frameworks and CI/CD pipelines to improve design productivity, regression efficiency, and quality tracking.
• Collaborate cross-functionally with design, CAD, verification, and physical implementation teams to optimize frontend workflows and silicon readiness.
• Identify methodology gaps and drive continuous improvement in design processes, tools, and infrastructure, including exploration of AI-assisted design techniques.
• Drive innovation in AI-enabled RTL design and frontend methodologies, evaluating opportunities for machine learning to enhance design quality, automation, and development efficiency.

Benefits

• Choice of three medical plan options
• Dental plan option
• Company credits towards medical and dental premiums
• 401(k) Plan with automatic 3% company contribution
• Ericsson match $1 for every $1 on the first 3% of eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay
• Company credits towards basic life insurance and basic accidental death and dismemberment coverage
• Company credits towards short-term and long-term disability coverage
• Option to participate in Ericsson’s Stock Purchase Plan
• 15 days of accrued vacation
• Up to 3 personal days per year
• 11 annual holidays
• 8 hours of volunteer time
• 80 hours of sick time annually
• Up to 16 weeks of paid maternity leave
• 6 weeks of parental or adoption leave at 100% of pay
• Financial wellness programs
• Educational assistance
• Matching gifts
• Recognition programs

What This Job Offers

• Job Type: Full-time
• Career Level: Principal