Experienced DFT ATPG Engineer

Intel Corporation•Waltham, MA

20h•$105,650 - $200,340•Hybrid

About The Position

The DFT ATPG engineer develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN). Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST). Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE). Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, testcoverage, DPM, and testtime/vectormemory reduction goals as well as design integrity for physical implementation. Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications. Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block. Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation. Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.

Requirements

BS EE/CE or related STEM field with 3+years of relevant DFT experience.
OR MS EE/CE or related STEM field with 1+years of relevant DFT experience.
1+ years of experience in tools like Siemens Tessent, Spyglass, Fusion compiler, and/or VCS is expected.
1+ years of experience with scan insertion, low coverage debug, GLS debug, and/or post silicon debug is expected.

Nice To Haves

Effective collaboration and communication skills to engage with cross-functional teams.
1+ years of experience with automatic test equipment (ATE) and working knowledge of test content generation for high-volume manufacturing will be a plus.
Strong problem-solving abilities to tackle complex design challenges.
Proven ability to drive innovation and continuous improvement in DFT methodologies and processes.
Passion for learning and contributing to cutting-edge semiconductor technologies.

Responsibilities

Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support.
Generates and delivers test content to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).
Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).
Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
Optimizes logic to qualify the design to meet power, performance, area, timing, testcoverage, DPM, and testtime/vectormemory reduction goals as well as design integrity for physical implementation.
Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.
Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block.
Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product.
Develops HVM content for rapid bring up and production on the ATE.