Design for Test Lead

Neurophos • Austin, TX

18d • Onsite

About The Position

Neurophos is developing a novel AI compute architecture using silicon photonics to overcome the power limitations of traditional electronic circuits. Our chips perform matrix multiplications at the speed of light, offering significantly higher energy efficiency and performance for AI inference. We have secured $110M in Series A funding and are looking for a DFT Architect to lead the design-for-test strategy for our electronic ICs. This is a key role where you will define test methodologies, assess coverage, and collaborate with RTL and physical design teams to integrate testability from the outset. You will also work with the analog team on their test requirements and manage the handoff to the post-silicon test program. This is a full-time, onsite position located in Austin, TX or Sunnyvale, CA.

Requirements

• 8 to 15 years in DFT, with hands-on ownership of scan, ATPG, and MBIST.
• Architect-level experience on a large digital ASIC: you've assessed a full chip, set the DFT strategy, and owned coverage signoff.
• Experience developing and specifying functional test vectors to augment structural coverage.
• Track record through tapeout on a complex compute ASIC.

Nice To Haves

• Analog test specification experience: defining what it takes to test analog circuits and working that out directly with the analog team.
• Cadence toolchain experience
• Exposure to silicon photonics test or design-for-test for photonic components.
• Experience using AI tooling in DFT flows.

Responsibilities

• Own DFT architecture and test control design for multiple ASIC devices using ATPG scan (stuck-at/at-speed), MBIST, and boundary scan / JTAG, including MCM and external HBM memory module DFT capabilities.
• Architect on-die memory test, including controller specification and generation, pattern selection, RAM grouping, and system test time and power analysis.
• Work with operations and PE teams to ensure all test modes are fully implemented, including HAST and other product qualification functions.
• Architect system-level wafer and package-level DFT plans for all phases of the product development process.
• Create and deploy integrated DFT development flow with critical metrics allowing quick analysis and updates to achieve near 100% test coverage.
• Own coverage assessment and signoff, including where to accept a coverage gap and the reasoning behind it.
• Develop and specify functional test vectors to augment structural coverage.
• Specify analog test requirements to the analog team, including self-test and loopback approaches.
• Build testability into RTL and implementation early, partnering with the RTL and physical design teams.
• Own handoff to the post-silicon test program, working with operations and package teams on where system-level validation picks up.
• Own delivery and deployment of production-level test plan to OSAT.

Benefits

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
• Unlimited PTO.
• 401(k) matching
• Stock option opportunities
• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
• Personalized Benefits: Choose the plans that fit your life and take the cash back for those that don’t.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed