Design Verification Technical Leader
About The Position
As part of Cisco’s Silicon One Optics group, the Design Verification Technical Leader will lead verification of high-speed silicon photonics driver ICs operating at 100/200/400G per Lambda. These ICs are integrated across Cisco routing, switching, and data center platforms, supporting optical transceivers and modules such as 800G and 1.6T products. The role defines verification methodology and standards across multiple projects and sites, leads block- and chip-level verification, contributes to specifications and design reviews, and influences architecture for testability and verification efficiency. It also includes mentoring verification engineers, debugging complex silicon and system-level issues during bring-up, and supporting post-silicon bring-up and integration and performance optimization.
Requirements
- Bachelor’s degree in Electrical or Computer Engineering and 8+ years of ASIC Design Verification experience; or a Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience; or a PhD in Electrical Engineering or Computer Engineering and 3+ years of ASIC Design Verification experience.
- Experience with SystemVerilog, UVM, and verification methodologies.
- Experience owning and delivering verification for large-scale SoCs or subsystems.
- Experience leading verification teams or projects.
- Experience with scripting and automation such as Python, Perl, TCL, or Shell Scripts.
Nice To Haves
- Strong experience with UVM for developing scalable, reusable, and coverage-driven verification environments.
- Expertise in verification of SerDes IP, D2D PHY IP, ODSP and integrated transceiver features, CPU subsystems, and protocols such as Ethernet, UCIE, UAL, SPI/I2C, etc.
- Experience influencing design for testability and verification.
- Proven experience in troubleshooting and debugging.
- Experience with Formal Verification and hardware description languages such as Verilog/SystemVerilog.
- Experience with emulation and prototyping platforms such as Veloce and HAPS.
- Experience collaborating with architecture and design teams on verification strategy.
Responsibilities
- Define and lead verification methodology and standards across multiple projects, coordinating activities across multiple sites.
- Lead block- and chip-level verification involving high-speed IPs, including ODSP, D2D IP, SerDes XSR/PAM4, integrated drivers/TIA, and control functions.
- Review specifications, participate in design reviews, and influence architecture for testability and verification efficiency.
- Mentor and coach verification engineers, promoting continuous improvement in technical skills and execution.
- Debug complex silicon and system-level issues during bring-up.
- Support post-silicon bring-up and optimize integration and performance.
- Collaborate with architecture and design teams on verification strategy.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) plan with Cisco matching contribution
- Paid parental leave
- Short- and long-term disability coverage
- Basic life insurance
- Paid holidays
- Floating holiday for non-exempt employees
- Paid day off for employee’s birthday
- Paid year-end holiday shutdown
- Paid personal wellness days
- Paid vacation or flexible vacation time off, depending on employee classification
- Sick time off
- Additional paid time away may be requested for critical or emergency family issues
- Optional paid volunteer days
- Annual bonuses for non-sales roles, subject to Cisco policies
- Employees may be eligible for Cisco restricted stock unit grants
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What This Job Offers
Job Type
Full-time
Career Level
Senior
