Design Verification Technical Leader
About The Position
Cisco’s Silicon One Optics group develops high-speed optical transceivers and modules, including 800G, 1.6T, and beyond, for AI/ML workloads and next-generation data centers. The Design Verification Technical Leader will lead verification of high-speed silicon photonics driver ICs operating at 100/200/400G per lane, integrated into Cisco routing, switching, and data center platforms. The role defines verification methods and standards across projects and sites, leads block- and chip-level verification, and works with architecture and design teams to improve testability and verification efficiency. It also includes mentoring verification engineers, debugging issues during bring-up, and supporting post-silicon integration and performance optimization.
Requirements
- Bachelor’s degree in Electrical or Computer Engineering and 8+ years of ASIC Design Verification experience; or a Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience; or a Ph.D. in Electrical Engineering or Computer Engineering and 3+ years of ASIC Design Verification experience.
- Experience with SystemVerilog, UVM, and verification methodologies.
- Experience owning and delivering verification for large-scale SoCs or subsystems.
- Experience leading verification teams or projects.
- Experience with scripting and automation, such as Python, Perl, TCL, or Shell scripts.
Nice To Haves
- Strong UVM experience developing scalable, reusable, coverage-driven verification environments.
- Expertise in verification of SerDes IP, D2D PHY IP, ODSP and integrated transceiver features, CPU subsystems, and protocols such as Ethernet, UCIE, UAL, and SPI/I2C.
- Experience influencing design for testability and verification.
- Proven troubleshooting and debugging experience.
- Experience with Formal Verification and HDLs such as Verilog/SystemVerilog.
- Experience with emulation and prototyping platforms such as Veloce and HAPS.
- Experience collaborating with architecture and design teams on verification strategy.
Responsibilities
- Define and lead verification methodology and standards across multiple projects, coordinating activities across multiple sites.
- Lead block- and chip-level verification for integrated high-speed IP, including ODSP, D2D IP, SerDes XSR/PAM4, integrated drivers/TIA, and control functions.
- Review specifications, participate in design reviews, and influence architecture for testability and verification efficiency.
- Mentor and coach verification engineers, promoting continuous improvement in technical skills and execution.
- Debug complex silicon and system-level issues during bring-up.
- Support post-silicon bring-up and optimize integration and performance.
- Collaborate with architecture and design teams on verification strategy.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) plan with Cisco matching contribution
- Paid parental leave
- Short- and long-term disability coverage
- Basic life insurance
- Cisco restricted stock unit grants may be available, subject to eligibility and vesting conditions.
- Paid holidays and a floating holiday for non-exempt employees
- Paid birthday day off, year-end holiday shutdown, and personal wellness days
- Paid vacation or flexible vacation time off, depending on employee classification
- Paid sick time
- Additional paid time away may be requested for critical or emergency family issues
- Optional paid volunteer days
- Annual bonuses may be available for non-sales roles, subject to Cisco policies
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What This Job Offers
Job Type
Full-time
Career Level
Senior
