Design Verification Engineering Lead - Silicon One
About The Position
Come join us and take part in shaping Cisco’s revolutionary solutions for data centers by designing some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world! As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You’ll architect and develop DV infrastructure, create and execute comprehensive test plans, and ensure robust verification and coverage for complex chips. Your collaboration with designers, architects, and software teams will help guarantee seamless integration and optimal performance of Cisco’s hardware platforms.
Requirements
- Typically: Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience
- Prior experience with Verilog, SystemVerilog, and UVM within the last 2-3 years.
- Prior experience with scripting languages (i.e Perl or Python)
- Prior experience with ASIC design and verification processes, debugging, methodology, and tools.
- Prior experience in verifying blocks/clusters or full chip level for ASIC.
Nice To Haves
- Experience with Linux, C/C++, and/or Python/Perl.
- Experience with Veloce/Palladium/Zebu/HAPS is a plus
- Post-silicon lab bring-up experience.
- Strong domain experience on one or more protocols – PCIe, Ethernet, RDMA, TCP, Fiber Channel (FC)
- Experience with Formal verification (iev/vc formal/Jasper Gold)
- Experience with AI agents (i.e Cursor, Codex, CoPilot, etc…)
- Lead verification for a complete SOC or ASIC is a plus
- Experience with Forwarding logic/Parsers/P4 is a plus
Responsibilities
- Architect block, cluster and top level DV environment infrastructure
- Create DV infrastructure from scratch for block, cluster and top-level environments
- Maintaining existing DV environments and enhancing them
- Ensuring complete verification coverage through implementation and review of code and functional coverage
- Working closely with ASIC designers
- Supporting tests done with emulation
- Work closely with software teams and debug issues found during firmware development
- Responsible for ASIC bring up
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- Cisco restricted stock units
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year (non-exempt)
- flexible vacation time off program (exempt)
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- up to 80 hours of unused sick time carried forward
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
- annual bonuses (for non-sales roles)
- performance-based incentive pay (for sales roles)
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What This Job Offers
Job Type
Full-time
Career Level
Senior
