Design Verification Engineering Intern - Bachelors
About The Position
As a Design Verification intern in this group, you will be responsible for developing detailed verification plans while working closely with the design and system team to ensure pre- silicon verification success. You will develop test benches, tests and simulations to DUT behavior, and run coverage regressions to meet the defined coverage goals for SystemVerilog functional coverage models of mixed-signal circuits for voltages and currents, real numbers, integers, and traditional digital functional coverage. You will track and communicate verification status, issues, and concerns, and work with regression tools and develop scripts to submit cases for regression analysis. You will utilize RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits, and constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus. You will contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows.
Requirements
- Bachelors degree
Responsibilities
- Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon verification success
- Developing test benches, tests and simulations to DUT behavior
- Running coverage regressions to meet the defined coverage goals for SystemVerilog functional coverage models of mixed-signal circuits for voltages and currents, real numbers, integers, and traditional digital functional coverage.
- Tracking and communicating verification status, issues, and concerns
- Work with regression tools and develop scripts to submit cases for regression analysis
- Utilize RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits.
- Constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus.
- Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows
Benefits
- competitive pay and benefits
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What This Job Offers
Job Type
Full-time
Career Level
Intern
