Design Verification Engineering Intern - Bachelors

Texas Instruments • Dallas, TX

4d

About The Position

As a Design Verification intern in this group, you will be responsible for developing detailed verification plans while working closely with the design and system team to ensure pre-silicon verification success. You will develop test benches, tests and simulations to DUT behavior, and run coverage regressions to meet the defined coverage goals for SystemVerilog functional coverage models of mixed-signal circuits for voltages and currents, real numbers, integers, and traditional digital functional coverage. You will track and communicate verification status, issues, and concerns, and work with regression tools and develop scripts to submit cases for regression analysis. You will utilize RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits. You will also work with constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus. Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows. Put your talent to work with us as a Design Engineer Intern – change the world, love your job!

Requirements

• Currently pursuing a Bachelors degree in Electrical Engineering, Computer Engineering or Electrical & Computer Engineering
• Cumulative 3.0/4.0 GPA or higher

Nice To Haves

• Ability to establish strong relationships with key stakeholders critical to success, both internally and externally
• Strong verbal and written communication skills
• Ability to quickly ramp on new systems and processes
• Demonstrated strong interpersonal, analytical and problem-solving skills
• Ability to work in teams and collaborate effectively with people in different functions
• Ability to take the initiative and drive for results
• Strong time management skills that enable on-time project delivery

Responsibilities

• Developing detailed verification plans while working closely with the design and system team to ensure pre-silicon verification success
• Developing test benches, tests and simulations to DUT behavior
• Running coverage regressions to meet the defined coverage goals for SystemVerilog functional coverage models of mixed-signal circuits for voltages and currents, real numbers, integers, and traditional digital functional coverage.
• Tracking and communicating verification status, issues, and concerns
• Work with regression tools and develop scripts to submit cases for regression analysis
• Utilize RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits.
• Constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus.
• Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows

What This Job Offers

• Career Level: Intern