Design Verification Engineer

Apple•Cupertino, CA

7d•$155,896 - $225,300•Hybrid

About The Position

Review SoC/IP/Subsystem specifications for system-on-chip(S0C), IP blocks, and subsystems to understand design requirements and expected functionality. Develop and maintain comprehensive test plans and coverage plans to ensure complete verification of hardware components. Write and execute simulation-based verification tests using hardware description and verification languages such as System Verilog. Collaborate closely with design and micro-architecture teams to clarify functionality, review new features, and align on test coverage goals. Debug simulation failures by analyzing waveforms, error logs, and internal signals to identify the root cause and assist in resolution. Track verification progress using internal project management tools, ensure all milestones are met, and test coverage metrics are updated regularly. Participate in recurring meetings and technical reviews to communicate progress, discuss challenges, and aligning tasks with team priorities Document test methodologies, debugging procedures, and verifying results to contribute to team knowledge and supporting ongoing development.

Requirements

Bachelor's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or related field and 3 years of experience in the job offered or related occupation.
3 years of experience in utilizing System Verilog for constrained random verification and functional coverage.
3 years of experience in utilizing UVM to develop verification environments and implement directed and random test cases.
3 years of experience in utilizing C and C++ to develop Verification IP including reference models and checkers.
3 years of experience in utilizing Python and Perl for creating automation tools, constraint generation, and regression analysis.
3 years of experience in utilizing EDA tools for testbench simulations, debugging, and coverage closure.
3 years of experience in utilizing High-speed interface protocols for verifying high bandwidth, low power data communication systems.
Utilizing Digital Design for understanding ASIC design flows and verification.
Utilizing Computer Architecture for exploration of memory subsystem and architecture trade-off analysis.

Responsibilities

Review SoC/IP/Subsystem specifications for system-on-chip(S0C), IP blocks, and subsystems to understand design requirements and expected functionality.
Develop and maintain comprehensive test plans and coverage plans to ensure complete verification of hardware components.
Write and execute simulation-based verification tests using hardware description and verification languages such as System Verilog.
Collaborate closely with design and micro-architecture teams to clarify functionality, review new features, and align on test coverage goals.
Debug simulation failures by analyzing waveforms, error logs, and internal signals to identify the root cause and assist in resolution.
Track verification progress using internal project management tools, ensure all milestones are met, and test coverage metrics are updated regularly.
Participate in recurring meetings and technical reviews to communicate progress, discuss challenges, and aligning tasks with team priorities.
Document test methodologies, debugging procedures, and verifying results to contribute to team knowledge and supporting ongoing development.