Design Verification Engineer

Apple•Cupertino, CA

1d•$129,300 - $194,700•Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Work closely with architecture and RTL designers on verifying the functionality correctness of the design. Develop and lead test plan and test environments. Develop complex tests in assembly, C, or vectors according to test plans. Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered. Develop checkers or C-base transactor to verify the design. Extend and maintain SystemVerilog/UVM testbenches. Monitor large-scale gate-level or RTL regressions. Inspect waveforms in Verdi or other hardware debugging tools. Write Python/ Perl utilities to scrub and aggregate regression data. Author and review detailed verification plans and coverage dashboards. Sync with cross-functional partners-architecture, validation, and firmware teams.

Requirements

Bachelor’s degree or foreign equivalent in Electrical Engineering and Computer Science, Computer Science, Electrical Engineering, Electronics Engineering, or a related field.
Utilizing digital logic design, computer architecture, and CPU microarchitecture concepts to verify CPU design.
Utilizing C++ and Verilog for testbench and test plan development.
Utilizing Verilog skills for assertion-based verification techniques.
Utilizing Verdi waveforms to debug functional issues in RTL, providing complete root cause analysis.
Developing random generators for stimulus to verify CPU microarchitecture features.
Hardware debugging and validation to identify, analyze, and resolve complex issues between components.
Providing verification of complex control logic structures to ensure the functionality correctness of the design.
Understanding computer architecture and CPU microarchitecture.

Responsibilities

Work closely with architecture and RTL designers on verifying the functionality correctness of the design.
Develop and lead test plan and test environments.
Develop complex tests in assembly, C, or vectors according to test plans.
Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered.
Develop checkers or C-base transactor to verify the design.
Extend and maintain SystemVerilog/UVM testbenches.
Monitor large-scale gate-level or RTL regressions.
Inspect waveforms in Verdi or other hardware debugging tools.
Write Python/ Perl utilities to scrub and aggregate regression data.
Author and review detailed verification plans and coverage dashboards.
Sync with cross-functional partners-architecture, validation, and firmware teams.