Design Verification Engineer

AppleCupertino, CA
Hybrid

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA.

Requirements

  • Utilizing System Verilog for constrained random verification and functional coverage.
  • Utilizing UVM to develop verification environments and implement directed and random test cases.
  • Utilizing C and C++ to develop Verification IP including reference models and checkers.
  • Utilizing Python and Perl for creating automation tools, constraint generation, and regression analysis.
  • Utilizing EDA tools for testbench simulations, debugging, and coverage closure.
  • Utilizing High-speed interface protocols for verifying high bandwidth, low power data communication systems.
  • Utilizing Digital Design for understanding ASIC design flows and verification.
  • Utilizing Computer Architecture for exploration of memory subsystem and architecture trade-off analysis.

Responsibilities

  • Review SoC/IP/Subsystem specifications for system-on-chip(S0C), IP blocks, and subsystems to understand design requirements and expected functionality.
  • Develop and maintain comprehensive test plans and coverage plans to ensure complete verification of hardware components.
  • Write and execute simulation-based verification tests using hardware description and verification languages such as System Verilog.
  • Collaborate closely with design and micro-architecture teams to clarify functionality, review new features, and align on test coverage goals.
  • Debug simulation failures by analyzing waveforms, error logs, and internal signals to identify the root cause and assist in resolution.
  • Track verification progress using internal project management tools, ensure all milestones are met, and test coverage metrics are updated regularly.
  • Participate in recurring meetings and technical reviews to communicate progress, discuss challenges, and aligning tasks with team priorities
  • Document test methodologies, debugging procedures, and verifying results to contribute to team knowledge and supporting ongoing development.

Benefits

  • Comprehensive medical and dental coverage
  • Retirement benefits
  • A range of discounted products and free services
  • Reimbursement for certain educational expenses — including tuition
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service