DMTS Design Engineering

GlobalFoundries • Austin, TX

7d • $166,500 - $290,000

About The Position

The Design Manager – Smart Analog & Sensors will lead the architecture, design, and execution of complex mixed-signal SoCs, with primary focus on digital subsystem design, IP integration, and end-to-end SoC realization for sensing-driven applications. This role emphasizes SoC creation, compute + control integration, and scalable IP-based development, enabling smart sensing platforms for automotive and industrial markets. The analog/sensor content is treated as a system integration component, while the core leadership spans digital architecture, RTL design, and SoC integration.

Requirements

• Digital subsystem design
• IP integration
• End-to-end SoC realization
• SoC creation
• Compute + control integration
• Scalable IP-based development
• Digital architecture
• RTL design
• SoC integration
• Hardware/software co-design
• RTL micro-architecture and implementation
• Subsystem integration and top-level assembly
• Lint, CDC, RDC, low-power intent (UPF)
• Synthesis and timing closure alignment with PD
• Silicon bring-up readiness and debug strategy
• System-level modeling and requirements definition flows
• Integrate analog/sensor subsystems (AFE, RF, data converters) into digital SoC framework
• Data path partitioning (analog vs digital vs software)
• Latency, power, and accuracy optimization

Nice To Haves

• Sensing-driven applications
• Smart sensing platforms for automotive and industrial markets
• Processor cores (e.g., RISC-V / MCU-class cores)
• DSP / ML accelerators
• Peripherals and connectivity IP
• IP reuse strategy and platformization
• Robust IP qualification, integration methodology, and interoperability verification
• Design Verification
• DFT
• Physical Design
• Product engineering
• System architecture
• Applications teams
• Functional correctness and coverage
• PPA (power, performance, area)
• Silicon bring-up readiness and debug strategy
• Analog/sensor content as a system integration component

Responsibilities

• Define and drive SoC architecture for Smart Sensor platforms, including compute subsystems (MCU / DSP / AI accelerators), interconnects (NoC, bus fabrics), memory subsystems and hierarchy, and control, security, and safety islands.
• Lead top-level SoC integration, partitioning functionality across digital, analog, and software domains.
• Drive hardware/software co-design, aligning system architecture with firmware and application requirements.
• Own development, selection, and integration of internal and 3rd-party IP, including processor cores (e.g., RISC-V / MCU-class cores), DSP / ML accelerators, and peripherals and connectivity IP.
• Define IP reuse strategy and platformization across multiple programs.
• Ensure robust IP qualification, integration methodology, and interoperability verification.
• Lead teams responsible for RTL micro-architecture and implementation, and subsystem integration and top-level assembly.
• Drive design best practices, including Lint, CDC, RDC, low-power intent (UPF), and synthesis and timing closure alignment with PD.
• Ensure high-quality handoff to DV, DFT, and Physical Design teams.
• Own delivery from specification → RTL → integration → tapeout → silicon bring-up.
• Partner closely with Design Verification, DFT, PD, and product engineering, as well as system architecture and applications teams.
• Drive closure on functional correctness and coverage, PPA (power, performance, area), and silicon bring-up readiness and debug strategy.
• Align execution with system-level modeling and requirements definition flows.
• Integrate analog/sensor subsystems (AFE, RF, data converters) into digital SoC framework.
• Drive system-level tradeoffs, including data path partitioning (analog vs digital vs software) and latency, power, and accuracy optimization.
• Ensure seamless interaction between sensor front-end, compute, and software stack.

Benefits

• Equal opportunity in the workplace
• Attraction and retention of highly qualified people
• Policies and processes pertaining to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law.

What This Job Offers

• Job Type: Full-time
• Career Level: Manager
• Education Level: No Education Listed