Design for Test (DFT) Engineer, Principal

Positron Corporation

4d•$200,000 - $350,000•Hybrid

About The Position

Positron AI is building next-generation AI inference accelerators, starting with our first ASIC, Asimov, with additional generations already underway. As Principal DFT Engineer, you'll own DFT and DFx strategy end-to-end: defining the DFT architecture for our accelerators, integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role spanning architecture through tapeout and into first silicon, not a coordination role.

Requirements

BS, MS, or PhD in Electrical Engineering or Computer Engineering
12+ years of ASIC development experience
Extensive hands-on DFT implementation experience on complex SoCs, with multiple successful production tapeouts
Strong understanding of scan architectures, ATPG, memory BIST, logic BIST, boundary scan, IJTAG, test compression, fault models, and structural coverage analysis
Experience with leading DFT tool suites (e.g., Siemens Tessent, Synopsys TestMAX DFT, Cadence Modus, or equivalent)
Strong RTL skills using Verilog/SystemVerilog
Experience with synthesis and gate-level verification
Strong scripting skills (Python, Tcl, Perl, or similar)
Excellent debugging skills across RTL, netlists, and silicon test
Demonstrated ability to drive technical execution across cross-functional engineering teams

Nice To Haves

Experience with high-performance AI accelerators, GPUs, CPUs, networking ASICs, PCIe, HBM, LPDDR, or chiplet architectures
High-speed SerDes and advanced process nodes (5nm and below)
Low-power design, yield enhancement methodologies, and manufacturing test optimization
Silicon bring-up, failure analysis, and post-silicon debug
Secure manufacturing and DFT: understanding of the interaction between secure boot, hardware root of trust, scan access control, fuse programming, key management, and production test
In-system debug and observability: experience architecting debug infrastructure (trace, event logging, test registers, scan visibility) that accelerates emulation and first-silicon bring-up
Emulation and pre-silicon validation: familiarity with Palladium/ZeBu/Veloce or FPGA prototyping to validate DFT features before tapeout
Third-party IP integration: experience auditing, integrating, and validating DFT collateral from multiple IP vendors to ensure a coherent full-chip DFT architecture, not just block-level stitching

Responsibilities

Own the Positron DFT strategy
Define and maintain the DFT architecture for Asimov and future ASIC generations.
Develop long-term DFT and DFx roadmaps aligned with product quality, manufacturing, yield, diagnostics, and reliability objectives.
Establish DFT design standards, review processes, signoff criteria, and best practices across the engineering organization.
Architect and implement scan insertion, compression, ATPG, memory BIST, logic BIST (where appropriate), boundary scan / IEEE 1149.x, IJTAG / IEEE 1687 infrastructure, and debug/observability features.
Integrate DFT into internally developed RTL.
Evaluate and integrate DFT capabilities from third-party IP providers.
Work directly in RTL, synthesis, and DFT tool flows.
Develop comprehensive DFT verification plans.
Validate DFT functionality through simulation and gate-level verification.
Ensure structural coverage targets are achieved before tapeout.
Drive DDA, stuck-at, transition, cell-aware, and power-aware ATPG strategies.
Own DFT signoff.
Work closely with backend implementation teams to ensure successful physical realization of DFT architecture.
Guide scan chain partitioning, compression planning, and test clock architecture.
Address power-aware test implementation, timing closure considerations, and test mode integration.
Serve as Positron's technical lead for all DFT work performed by external design services partners.
Review implementation quality and conduct design reviews.
Drive issue resolution.
Define deliverables and acceptance criteria.
Ensure external work meets Positron quality standards.
Partner closely with RTL designers, design verification, physical design, package and test engineering, firmware, system software, and silicon validation to ensure DFT is designed in from architecture through silicon bring-up.
Leverage modern AI tools to improve engineering productivity, including automated review of DFT reports, ATPG analysis, coverage analysis, regression triage, documentation generation, workflow automation, and agentic engineering assistants.
Continuously evaluate new AI techniques that accelerate DFT development while improving quality.