DFT Design Engineer

Intel Corporation•Fort Collins, CO

5d•$105,650 - $149,150•Hybrid

About The Position

As a DFT Design Engineer, you will play a vital role in shaping the quality and performance of Intel's silicon products. You will contribute to the development of cutting-edge technologies by designing and verifying robust Design for Test (DFT) features that ensure manufacturability and reliability. Your work will directly impact Intel's ability to deliver high-quality products to market quickly, meeting both performance and quality objectives. This position offers the opportunity to collaborate with cross-functional teams, influence design methodologies, and drive innovation in test strategies for SoC and functional IP blocks.

Requirements

Bachelor’s degree in computer or electrical engineering, or a related field with no prior experience required.
6+ months of experience with design tools
6+ months with RTL coding and DFT techniques.

Nice To Haves

Master's in computer engineering or computer science with 6+ months of experience
Familiarity with test architecture including SCAN, MBIST, BSCAN, and TAP.
Familiarity with RTL coding, DFT techniques, and timing closure methods.
Experience with design tools and methodologies such as ATPG and coverage analysis.
Experience configuring EDT setups and resolving stuck-at and at-speed test scenarios.
Proficient programming skills in TCL, Python, Perl, and/or C++.
Knowledge of GLS for test scenario resolution and ATPG coverage analysis
Strong communication and collaboration skills, with a focus on teamwork across diverse engineering groups.

Responsibilities

Develop logic design, register transfer level (RTL) coding, and implement DFT architectures including SCAN, MBIST, BSCAN, and TAP.
Collaborate in the definition of architecture and microarchitecture features for DFT blocks and subsystems.
Optimize logic to achieve power, performance, area, timing, test coverage, and defect per million (DPM) goals.
Write and generate RTL and structural code for DFT integration, ensuring design integrity for physical implementation.
Review and execute verification plans to ensure design features meet architecture specifications.
Resolve RTL test failures and implement corrective measures to ensure feature correctness.
Support SoC customers for successful integration of DFT blocks, contributing to high-quality IP and SoC designs.
Develop high-volume manufacturing (HVM) test content for rapid bring-up and production deployment on automatic test equipment (ATE).
Collaborate with post-silicon and manufacturing teams to verify features in silicon and support debugging requirements.